• Title/Summary/Keyword: Si-V defect

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Partial Discharge Characteristics of void in Nano-composites Materials (나노복합재료의 보이드 부분방전 특성)

  • Jeong, I.B.;Choi, H.M.;Kim, W.J.;Cho, K.S.;Choi, K.J.;Kim, J.H.;Yeon, K.H.;Hong, J.W.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.397-398
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    • 2009
  • In oder to investigate of partial discharge of nano-composites materials, we have studied partial discharge appling voltage from 5 to 30 [kV] to make an artificial defect with the epoxy adding to 0, 0.4, 0.8, and 1.6 [wt%], respectively. The experimental result, we have found that $SiO_2$ of 0.4 (wt%] was superior to others also, it is found that the effect of isolate diagnosis to get the slope for the discharged electric charge distribution.

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The Study of Deep Level Behaviors in Si Contaminated by Iron (Fe 오염에 따른 Si내의 deep level거동에 관한 연구)

  • Mun, Yeong-Hui;Kim, Jong-O
    • Korean Journal of Materials Research
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    • v.9 no.1
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    • pp.104-107
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    • 1999
  • We investigated the effects of cooling condition on deep levels and iron precipitate formation in iron-contaminated p-type silicon by DLTS(Deep Level Transient Spectroscopy) and preferential etching technique. Dependency of cooling condition on Bulk Micro-Defect (BMD) and four different iron-related deep traps were observed. For normal cooling condition, T1, T2, T3, T4 traps that related to Fe\ulcorner or Fe-O complex were obtained. However, the trap with activation energy, 0.4 eV was observed for slow cooling condition. The trap caused by the $\textrm{Fe}^{+}\textrm{}^{-}$ pair (H4:0.56eV) were detected only at the case of $\textrm{LN}_{2}$ quenching condition.

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Preparation of the SiO2 Films with Low-Dit by Low Temperature Oxidation Process (저온 산화공정에 의해 낮은 Dit를 갖는 실리콘 산화막의 제조)

  • Jeon, Bup-Ju;Jung, Il-Hyun
    • Applied Chemistry for Engineering
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    • v.9 no.7
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    • pp.990-997
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    • 1998
  • In this work, the $SiO_2$ films on the silicon substrate with different orientations were first prepared by the low temperature process using the ECR plasma diffusion as a function of microwave power and oxidation time. Before and after thermal treatment, the surface morphology, Si/O ratio from physicochemical properties, and the electrical properties of the oxide films were also investigated. The oxidation rate increased with microwave power, while surface morphology showed the nonuniform due to etching. The film quality, therefore, was lowered with increasing the defect by etching and the content of positive oxide ions in the oxide films from bulk by higher self-DC bias. The content of positive oxide ions in the oxide films with different Si orientations showed Si(100) < Si(111) < poly Si. The defects in $Si/SiO_2$ interface of $SiO_2$ film could be decreased by annealing, while $Q_{it}$ and $Q_f$ were independent of thermal treatment and the dependent on concentration of reactive oxide ions and self-DC bias of substrate. At microwave power of 300, and 400 W, the high quality $SiO_2$ film that had lower surface roughness and defect in $Si/SiO_2$ interface was obtained. The value of interface trap density, then, was ${\sim}9{\times}10^{10}cm^{-2}eV^{-1}$.

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Preparation and Electronic Defect Characteristics of Pentacene Organic field Effect Transistors

  • Yang, Yong-Suk;Taehyoung Zyung
    • Macromolecular Research
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    • v.10 no.2
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    • pp.75-79
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    • 2002
  • Organic materials have considerable attention as active semiconductors for device applications such as thin-film transistors (TFTs) and diodes. Pentacene is a p-type organic semiconducting material investigated for TFTs. In this paper, we reported the morphological and electrical characteristics of pentacene TFT films. The pentacene transistors showed the mobility of 0.8 $\textrm{cm}^2$/Vs and the grains larger than 1 ${\mu}{\textrm}{m}$. Deep-level transient spectroscopy (DLTS) measurements were carried out on metal/insulator/organic semiconductor structure devices that had a depletion region at the insulator/organic-semiconductor interface. The duration of the capacitance transient in DLTS signals was several ten of seconds in the pentacene, which was longer than that of inorganic semiconductors such as Si. Based on the DLTS characteristics, the energy levels of hole and electron traps for the pentacene films were approximately 0.24, 1.08, and 0.31 eV above Ev, and 0.69 eV below Ec.

High Current Stress characteristics on Sequential Lateral Solidification (SLS) Poly-Si TFT

  • Jung, Kwan-Wook;Kim, Ung-Sik;Kang, Myoung-Ku;Choi, Pil-Mo;Lee, Su-Kyeong;Kim, Hyun-Jae;Kim, Chi-Woo;Jung, Kyu-Ha
    • 한국정보디스플레이학회:학술대회논문집
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    • 2003.07a
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    • pp.673-674
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    • 2003
  • The reliability of TFT, crystallized by sequential lateral solidification (SLS) technology, has been studied High current damage is characterized by high gate bias (-20V) and drain bias (-10V). It is found that performance of SLS TFTs is enhanced by high current stress up to 300 sec of stress time for 20/8 (W/L) N-TFT. After that, TFT performance is degraded with the increase of the stress time. It is speculated from the experimental data that SLS TFTs initially contain a number of unstable defect states. Then, the defect states seem to be cured by high current stress.

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Silicon Nitride Films Prepared at a Low Temperature (${\leq}200^{\circ}C$) for Gate Dielectric of Flexible Display

  • Lee, Kyoung-Min;Hwang, Jae-Dam;Lee, Youn-Jin;Hong, Wan-Shick
    • 한국정보디스플레이학회:학술대회논문집
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    • 2009.10a
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    • pp.1402-1404
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    • 2009
  • The silicon nitride films for gate dielectric were deposited by catalytic chemical vapor deposition at low temperature (${\leq}200^{\circ}C$). The mixture of $SiH_4$, $NH_3$ and $H_2$ was used as source gases. The current-voltage (I-V) and the capacitance-voltage (C-V) characteristics of the films were measured. The breakdown voltage and the flat band voltage shift of samples were improved by increase of the $NH_3$ contents and $H_2$ dilution ratio. The defect states were analyzed by photoluminescence (PL) spectra. As the defect states decreased, the breakdown voltage and the flat band voltage shift increased.

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Effect of Alternate Bias Stress on p-channel poly-Si TFT`s (P-채널 다결정 실리콘 박막 트랜지스터의 Alternate Bias 스트레스 효과)

  • 김영호;조봉희;강동헌;길상근;임석범;임동준
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.14 no.11
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    • pp.869-873
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    • 2001
  • The effects of alternate bias stress on p-channel poly-Si TFT\`s has been systematically investigated. We alternately applied positive and negative bias stress on p-channel poly-Si TFT\`s, device Performance(V$\_$th/, g$\_$m/, leakage current, S-slope) are alternately appeared to be increasing and decreasing. It has been shown that device performance degrade under the negative bias stress while improve under the positive bias stress. This effects have been related to the hot carrier injection into the gate oxide rather than the generation of defect states within the poly-Si/SiO$_2$ interface under alternate bias stress.

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Computer Simulaton of Defect Formation Behaviors of Crystal-Silicon on the Low Energy Arsenic Implantation by Molecular Dynamics (분자동력학적 방법에 의한 저 메너지 As 이온 주입에 따른 Si 기판의 결함 형성 거동에 대한 컴퓨터 모사 실험)

  • Chung, Dong-Seok;Park, Byung Do
    • Journal of the Korean Society for Heat Treatment
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    • v.13 no.4
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    • pp.259-264
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    • 2000
  • In this study, we quantitatively measure the ion ranges of arsenic with energies ranging from 10 KeV to 100 KeV, implanted at $3^{\circ}$, $9^{\circ}$ $15^{\circ}$ the (100) plane, and the damage created during ion implantation. To obtain detailed information of ion range and damage distributions in low energy region where elastic collisions dominate the slowing down process, molecular dynamics computer simulation was performed and compared to the existing results. The effects of implant energy and degree on damage generation are present. The number of vacancy were calculated from the deposited energy using Kinchin-Pease equation. In the energy range 10 keV-100 keV, simulations show that the number of Frenckel pairs produced by As-ion bimbardment is 9 and incident angle dependence of the vacancy was the same but defects were distributed at different depth.

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Effect of Oxygen Mixture Ratio on the Properties of ZnO Thin-Films and n-ZnO/p-Si Heterojunction Diode Prepared by RF Sputtering (산소 혼합 비율에 따른 RF 스퍼터링 ZnO 박막과 n-ZnO/p-Si 이종접합 다이오드의 특성)

  • Gwon, Iksun;Kim, Danbi;Kim, Yewon;Yeon, Eungbum;Kim, Seontai
    • Korean Journal of Materials Research
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    • v.29 no.7
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    • pp.456-462
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    • 2019
  • ZnO thin-films are grown on a p-Si(111) substrate by RF sputtering. The effects of growth temperature and $O_2$ mixture ratio on the ZnO films are investigated by scanning electron microscopy (SEM), X-ray diffraction (XRD), and room-temperature photoluminescence (PL) measurements. All the grown ZnO thin films show a strong preferred orientation along the c-axis, with an intense ultraviolet emission centered at 377 nm. However, when $O_2$ is mixed with the sputtering gas, the half width at half maximum (FWHM) of the XRD peak increases and the deep-level defect-related emission PL band becomes pronounced. In addition, an n-ZnO/p-Si heterojunction diode is fabricated by photolithographic processes and characterized using its current-voltage (I-V) characteristic curve and photoresponsivity. The fabricated n-ZnO/p-Si heterojunction diode exhibits typical rectifying I-V characteristics, with turn-on voltage of about 1.1 V and ideality factor of 1.7. The ratio of current density at ${\pm}3V$ of the reverse and forward bias voltage is about $5.8{\times}10^3$, which demonstrates the switching performance of the fabricated diode. The photoresponse of the diode under illumination of chopped with 40 Hz white light source shows fast response time and recovery time of 0.5 msec and 0.4 msec, respectively.

Influence of Co-sputtered HfO2-Si Gate Dielectric in IZO-based thin Film Transistors (HfO2-Si의 조성비에 따른 HfSiOx의 IZO 기반 산화물 반도체에 대한 연구)

  • Cho, Dong Kyu;Yi, Moonsuk
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.2
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    • pp.98-103
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    • 2013
  • In this work, we investigated the enhanced performance of IZO-based TFTs with $HfSiO_x$ gate insulators. Four types of $HfSiO_x$ gate insulators using different diposition powers were deposited by co-sputtering $HfO_2$ and Si target. To simplify the processing sequences, all of the layers composing of TFTs were deposited by rf-magnetron sputtering method using patterned shadow-masks without any intentional heating of substrate and subsequent thermal annealing. The four different $HfSiO_x$ structural properties were investigated x-ray diffraction(XRD), atomic force microscopy(AFM) and also analyzed the electrical characteristics. There were some noticeable differences depending on the composition of the $HfO_2$ and Si combination. The TFT based on $HfSiO_x$ gate insulator with $HfO_2$(100W)-Si(100W) showed the best results with a field effect mobility of 2.0[$cm^2/V{\cdot}s$], a threshold voltage of -0.5[V], an on/off ratio of 5.89E+05 and RMS of 0.26[nm]. This show that the composition of the $HfO_2$ and Si is an important factor in an $HfSiO_x$ insulator. In addition, the effective bonding of $HfO_2$ and Si reduced the defects in the insulator bulk and also improved the interface quality between the channel and the gate insulator.