• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2011.05a
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• pp.155-155
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• 2011

Dual coil을 사용하는 상용 AMAT DPS II 300 mm Centura 장비의 antenna의 전류비를 조절하여 $SiO_2$의 식각 균일도를 평가하였다. Inner turn과 outer turn의 흐르는 전류비를 분배 capacitor로 조절하여 16.9 %의 이온 전류 밀도 분포를 확인하였고, 투입 전력에 따라 200 W에서 12 %, 800 W에서 9 %로 점차 감소하는 경향을 확인하였다. 이때 300 mm wafer의 반지름 방향으로의 식각 균일도는 3 %로 측정되었고, FRC (flow ratio control)는 0.5에서 가장 균일한 결과를 얻었다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.10a
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• pp.171-172
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• 2009

TSV(through via silicon)를 이용한 Via의 Cu 충전에서 Seed 층의 역할은 전류의 흐름을 가능하게 하는 중요한 역할을 하고 있다. Via에 각각 Ti/Au, Ti/Cu를 증착한 후 Ti/Cu가 Ti/Au를 대체 할 수 있는지를 알아보기 위해 먼저 실리콘 웨이퍼에 via를 형성하고, 형성된 via에 기능성 박막층으로 절연층(SiO2) 및 시드층을 형성하였다. 전해도금을 이용하여 Cu를 충전한 결과 Ti/Au 및 Ti/Cu를 증착한 두 시편 모두 via와 seed층 접합면에 박리 등의 결함이 없었고, via 내부 또한 void나 seam 등이 관찰되지 않고 우수하게 충전된 것을 확인할 수 있었다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.165-165
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• 2003

The growth of GaN on Si is of great interest due to the several advantages low cost, large size and high-quality wafer availability as well as its matured technology. The crystal quality of GaN is known to be much influenced by the surface pretreatment of Si substrate [1]. In this work, the properties of GaN overlayer grown on ion implanted Si(111)and bare Si(111) have been investigated. Si(111) surface was treated ion implantation with 60KeV and dose 1${\times}$10$\^$16//$\textrm{cm}^2$ prior to film growth. GaN epilayers were grown at 1100$^{\circ}C$ for 1 hour after growing AlN buffer layers for 15-30 minutes at 1100$^{\circ}C$ with metal organic chemical vapor deposition (MOCVD). The properties of GaN epilayers were evaluated by X-Ray Diffraction (XRD), Scanning electron microscope (SEM) Photoluminescence (PL) at room temperature and Hall measurement The results showed that the GaN on ion implanted Si(111) markedly affected to the structural, optical and electrical characteristic of GaN layers.

• Clean Technology
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• v.7 no.3
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• pp.215-223
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• 2001

A present semiconductor cleaning technology is based upon RCA cleaning technology which consumes vast amounts of chemicals and ultra pure water(UPW) and is the high temperature process. Therefore, this technology gives rise to the many environmental issues, and some alternatives such as electrolyzed water(EW) are being studied. In this work, intentionally contaminated Si wafers were cleaned using the electrolyzed water. The electrolyzed water was generated by an electrolysis system which consists of three anode, cathode, and middle chambers. Oxidative water and reductive water were obtained in anode and cathode chambers, respectively. In case of NH4Cl electrolyte, the oxidation-reduction potential and pH for anode water(AW) and cathode water(CW) were measured to be +1050mV and 4.8, and -750mV and 10.0, respectively. AW and CW were deteriorated after electrolyzed, but maintained their characteristics for more than 40 minutes sufficiently enough for cleaning. Their deterioration was correlated with CO2 concentration changes dissolved from air. Contact angles of UPW, AW, and CW on DHF treated Si wafer surfaces were measured to be $65.9^{\circ}$, $66.5^{\circ}$ and $56.8^{\circ}$, respectively, which characterizes clearly the eletrolyzed water. To analyze the amount of metallic impurities on Si wafer surface, ICP-MS was introduced. It was known that AW was effective for Cu removal, while CW was more effective for Fe removal. To analyze the number of particles on Si wafer surfaces, Tencor 6220 were introduced. The particle distributions after various particle removal processes maintained the same pattern. In this work, RCA consumed about $9{\ell}$ chemicals, while EW did only $400m{\ell}$ HCl electrolyte or $600m{\ell}$ NH4Cl electrolyte. It was hence concluded that EW cleaning technology would be very effective for promoting environment, safety, and health(ESH) issues in the next generation semiconductor manufacturing.

• Journal of the Korean Vacuum Society
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• v.17 no.3
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• pp.199-203
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• 2008

The effects of surface treatment by $O_2$ plasma on the Bio-FETs were investigated by using the pseudo-MOSFETs on the SOI substrates. After a surface treatment by $O_2$ plasma with different RF powers, the current-voltage and field effect mobility of pseudo-MOSFETs were measured by applying back gate bias. The subthreshold characteristics of pseudo-MOSFETs were significantly degraded with increase of RF power. Additionally, a forming gas anneal process in 2 % diluted $H_2/N_2$ ambient was developed to recover the plasma process induced surface damages. A considerable improvement of the subthreshold characteristics was achieved by the forming gas anneal. Therefore, it is concluded that the pseudo-MOSFETs are a powerful tool for monitoring the surface treatment of Bio-FETs and the forming gas anneal process is effective for improving the electrical characteristics of Bio-FETs.

• Tribology and Lubricants
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• v.19 no.2
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• pp.109-115
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• 2003

Nanotribological characteristics between a Si$_3$N$_4$ AFM tip and hydrophobic thin films were experimentally studied. Tests were performed to measure the nano adhesion and friction in both AFM (atomic force microscope) and LFM (lateral force microscope) modes in various .ranges of normal load. Plasma-modified thin polymeric films were deposited on Si-wafer (100). Results showed that wetting angle of plasma-modified thin polymeric film increased with the treating time, which resulted in the hydrophobic surface and the decrease of adhesion and friction. Nanotribological characteristics of these surfaces were compared with those of other hydrophobic surfaces, such as DLC, OTS and IBAD-Ag coated surfaces. Those of OTS coated surface were superior to those of others, though wetting angle of plasma-modified thin polymeric film is higher.

• Korean Journal of Materials Research
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• v.11 no.5
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• pp.427-430
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• 2001

We prepared 10cm-diameter Si(100)/500 $\AA$-Si$_3$N$_4$/Si(100) wafer Pairs adopting 500 $\AA$ -thick Si$_3$N$_4$layer as insulating layer between single crystal Si wafers. Si3N, is superior to conventional SiO$_2$ in insulating. We premated a p-type(100) Si wafer and 500 $\AA$ -thick LPCVD Si$_3$N$_4$∥Si (100) wafer in a class 100 clean room. The cremated wafers are separated in two groups. One group is treated to have hydrophobic surface and the other to have hydrophilic. We employed a FLA(fast linear annealing) bonder to enhance the bond strength of cremated wafers at the scan velocity of 0.1mm/sec with varying the heat input at the range of 400~1125W. We measured bonded area using a infrared camera and bonding strength by the razor blade crack opening method. We used high resolution transmission electron microscopy(HRTEM) to probe cross sectional view of bonded wafers. The bonded area of two groups was about 75%. The bonding strength of samples which have hydrophobic surface increased with heat input up to 1577mJ/$m^2$ However, bonding strength of samples which have hydrophilic surface was above 2000mJ/$m^2$regardless of heat input. The HRTEM results showed that the hydrophilic samples have about 25 $\AA$ -thick SiO layer between Si and Si$_3$N$_4$/Si and that maybe lead to increase of bonding strength.

• Korean Journal of Materials Research
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• v.21 no.12
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• pp.666-672
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• 2011

The a-Si:H/c-Si hetero-junction (HJ) solar cells have a variety of advantages in efficiency and fabrication processes. It has already demonstrated about 23% in R&D scale and more than 20% in commercial production. In order to further reduce the fabrication cost of HJ solar cells, fabrication processes should be simplified more than conventional methods which accompany separate processes of front and rear sides of the cells. In this study, we propose a simultaneous deposition of intrinsic thin a-Si:H layers on both sides of a wafer by dual hot wire CVD (HWVCD). In this system, wafers are located between tantalum wires, and a-Si:H layers are simultaneously deposited on both sides of the wafer. By using this scheme, we can reduce the process steps and time and improve the efficiency of HJ solar cells by removing surface contamination of the wafers. We achieved about 16% efficiency in HJ solar cells incorporating intrinsic a-Si:H buffers by dual HWCVD and p/n layers by PECVD.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2014.11a
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• pp.230-230
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• 2014

디지털 홀로그램 이미징 장치를 이용하여 박막과 웨이퍼 간의 두께 및 하전입자의 분포를 모니터링하는 센서의 성능을 보고한다. 이 센서는 웨이퍼와 SiN 박막 간의 경계를 구분하였으며, 경계에서의 하전입자의 분포의 분석도 가능함을 보였다. 이 센서는 다양한 종류의 계면 내지 박막 내부의 하전입자의 분포의 측정을 가능하게 하며, 또한 두께 변이의 실시간 측정도 가능하게 하여 향후 대량 생산현장에서의 광범위한 응용이 예상된다.

• Journal of the Korean Ceramic Society
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• v.46 no.6
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• pp.685-688
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• 2009

Surface Texturing is very important process for high cell efficiency in crystalline silicon solar cell. Anisotropic texturing with an alkali etchant was known not to be able to produce uniform surface morphology in multi-crystalline silicon (mc-Si), because of its different etching rate with random crystal orientation. In order to reduce surface reflectance of mc-Si wafer, the general etching tendency was studied with HF/HN$O_3$/De-ionized Water acidic solution. And the surface structures of textured mc-Si in various HF/HN$O_3$ ratios were compared. The surface morphology and reflectance of textured silicon wafers were measured by FE-SEM and UVvisible spectrophotometer, respectively. We obtained average reflectance of $16{\sim}19$% for wavelength between 400 nm and 900 nm depending on different etching conditions.