• Journal of Industrial and Engineering Chemistry
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• v.67
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• pp.417-428
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• 2018

In this study, we fabricated hierarchically self-assembled thin films composed of graphene oxide (GO) sheets and gold nanoparticles (Au NPs) using the Langmuir-Blodgett (LB) and Langmuir-Schaefer (LS) techniques and investigated their gas-sensing performance. First, a thermally oxidized silicon wafer ($Si/SiO_2$) was hydrophobized by depositing the LB films of cadmium arachidate. Thin films of ligand-capped Au NPs and GO sheets of the appropriate size were then sequentially transferred onto the hydrophobic silicon wafer using the LB and the LS techniques, respectively. Several different films were prepared by varying the ligand type, film composition, and surface pressure of the spread monolayer at the air/water interface. Their structures were observed by scanning electron microscopy (SEM) and atomic force microscopy (AFM), and their gas-sensing performance for $NH_3$ and $CO_2$ was assessed. The thin films of dodecanethiol-capped Au NPs and medium-sized GO sheets had a better hierarchical structure with higher uniformity and exhibited better gas-sensing performance.

• ETRI Journal
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• v.19 no.1
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• pp.26-35
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• 1997

The substrate effects on solid-phase crystallization of amorphous silicon (a-Si) films deposited by low-pressure chemical vapor deposition (LPCVD) using $Si_2H_6$ gas have been extensively investigated. The a-Si films were prepared on various substrates, such as thermally oxidized Si wafer ($SiO_2$/Si), quartz and LPCVD-oxide, and annealed at 600$^{\circ}C$ in an $N_2$ ambient for crystallization. The crystallization behavior was found to be strongly dependent on the substrate even though all the silicon films were deposited in amorphous phase. It was first observed that crystallization in a-Si films deposited on the $SiO_2$/Si starts from the interface between the a-Si and the substrate, so called interface-interface-induced crystallization, while random nucleation process dominates on the other substrates. The different kinetics and mechanism of solid-phase crystallization is attributed to the structural disorderness of a-Si films, which is strongly affected by the surface roughness of the substrates.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1305-1306
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• 2007

To lower the fabrication cost of silicon solar cells, a surface treatment using a dielectric barrier discharge instead of a wet cleaning technique was examined on electrode surfaces on silicon solar cells. The fill factor obtained through measuring current-voltage characteristics was evaluated, and the treated surface state was characterized by energy-dispersive X-ray. It was found that the dielectric barrier discharge effectively activated the electrode surface and the surface treatment on finger electrodes contributed greatly to improve the fill factor.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.407-410
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• 2002

Thermal oxidations of 3C-SiC thin-films grown on Si(100) by APCVD(atmospheric pressure chemical vapor deposition) were carried out. The oxidations of 3C-SiC were performed at $1100^{\circ}C$ for 1~6 hr in wet and dry $O_2$ ambient, respectively. Ellipsometry was used to determine the thickness and index of refraction of oxide films. The oxide thickness vs. the oxidation time follows the general relationship used for the thermal oxidation of Si. The surface roughness was analyzed by using AFM(atomic force microscopy). The surface roughness of oxidized 3C-SiC was rougher than before oxidation. The thermal oxide was found to be $SiO_2$ by XPS(X-ray photoelectron spectroscopy) analysis. Auger analysis showed them to be homogeneous with near stoichiometric composition.

• Proceedings of the Materials Research Society of Korea Conference
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• 1996.11a
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• pp.108-109
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• 1996

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.11
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• pp.841-845
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• 2013

We give a textured front on silicon wafer for high-efficiency solar cells by using micro contact printing method which uses PDMS (polydimethylsiloxane) silicon rubber as a stamp and SAM (self assembled monolayer)s as an ink. A random pyramidal texturing have been widely used for a front-surface texturing in low cost manufacturing line although the cell with random pyramids on front surface shows relatively low efficiency than the cell with inverted pyramids patterned by normal optical lithography. In the past two decades, the micro contact printing has been intensively studied in nano technology field for high resolution patterns on silicon wafer. However, this promising printing technique has surprisingly never applied so far to silicon based solar cell industry despite their simplicity of process and attractive aspects in terms of cost competitiveness. We employ a MHA (16-mercaptohexadecanoic acid) as an ink for Au deposited $SiO_2/Si$ substrate. The $SiO_2$ pattern which is same as the pattern printed by SAM ink on Au surface and later acts as a hard resist for anisotropic silicon etching was made by HF solution, and then inverted pyramidal pattern is formed after anisotropic wet etching. We compare three textured surface with different morphology (random texture, random pyramids and inverted pyramids) and then different geometry of inverted pyramid arrays in terms of reflectivity.

• Journal of the Korean institute of surface engineering
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• v.47 no.2
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• pp.75-80
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• 2014

Nanocrystalline diamond(NCD) films on steel(SKH51) has been investigated using SiC interlayer film. SiC was deposited on SKH51 or Si wafer by RF magnetron sputter. NCD was deposited on SiC at $600^{\circ}C$ for 0.5~4 h employing microwave plasma CVD. Film morphology was observed by FESEM and FIB. Film adherence was examined by Rockwell C adhesion test. The growth rate of NCD on SiC/Si substrate was much higher than that on SiC/SKH51. During particle coalescence, NCD growth rate was slow since overall rate was determined by the diffusion of carbon on SiC surface. After completion of particle coalescence, NCD growth became faster with the reaction of carbon on NCD film controlling the whole process. In the case of SiC/SKH51 substrate, a complete NCD film was not formed even after 4 h of deposition. The adhesion test of NCD/SiC/SKH51 samples revealed a delamination of film whereas that of SiC/SKH51 showed a good adhesion. Many voids of less than 0.1 ${\mu}m$ were detected on NCD/SiC interface. These voids were believed as the reason for the poor adhesion between NCD and SiC films. The origin of voids was due to the insufficient coalescence of diamond particles on SiC surface in the early stage of deposition.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.19-22
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• 2007

반도체 산업은 회로의 고밀도화, 고집적화에 따라 웨이퍼 표면의 입자, 금속, 금속 이온, 유기물 등 오염물의 크기가 미세해 지고 세정에 대한 요구 조건이 더욱 엄격해지고 있다. 현재 세정 공정은 반도체 제조공정 전체에서 약 30%를 차지하고 있으며, 습식 세정 방식이 주로 사용되고 있다.[1] 습식 세정방식은 탈이온수로 린스하고 건조하는 공정이 필연적으로 따르며, 기판 표면에 건조과정에서 물반점이 남는 문제가 가장 큰 이슈로 남아 있다. 본 연구는 웨이퍼의 습식 세정 공정에 사용되는 DHF Final Clean Process후 IPA Vapor를 이용한 건조 방법을 기술 하였다. Single wafer spin process를 이용하였으며, 웨이퍼 Process 공간을 밀폐 후 N2가스를 충진하여 대기중의 산소 오염원 유입을 차단하고 수세 및 건조 가스를 이용하여 건조시킴으로써 SiFx의 SiOx로의 치환을 방지 하여 건조 효율 향상을 목적으로 한다. Bare 웨이퍼에서 65nm 이상 오염 발생 증가량을 측정 하였으며, 공정 후 웨이퍼 오염 발생량을 35개 이하로 확보 하였다.

• Journal of Sensor Science and Technology
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• v.13 no.4
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• pp.264-269
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• 2004

This paper describes on an advanced technology of 3C-SiC/Si(100) wafer direct bonding using PECVD oxide to intermediate layer for SiCOI(SiC-on-Insulator) structure because it has an attractive characteristics such as a lower thermal stress, deposition temperature, more quick deposition rate and higher bonding strength than common used poly-Si and thermal oxide. The PECVD oxide was characterized by ATR-FTIR. The bonding strength with variation of HF pre treatment condition was measured by tensile strength measurement system. After etch-back using TMAH solution, roughness of 3CSiC surface crystallinity and bonded interface was measured and analyzed by AFM, XRD, and SEM respectively.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.9
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• pp.672-675
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• 1999

Si-to-Si electrostatic bonding was carried out by employing LSG interlayer instead of conventional Corning #7740 interlayer in order to improve bonding properties. The surface roughness and dielectric breakdown field of the LSG interlayers deposited on Si substrates were investigated. Also, the bonding interface, bonding strength and bonding mechanism were discussed for the electrostatically-bonded Si-Si wafer pairs having LSG interlayers.