• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1991.10a
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• pp.63-67
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• 1991

Amorphous silicon films were deposited on glass, [100] single crystal silicon wafer with thermally grown silicon dioxide, and [100] silicon wafer substrates by Plasma Enhanced Chemical Vapor Deposition(with argon diluted silane source gas). Growth rate, UV optical band edge, and the hydrogen quantity in the amorphous silicon films have been investigated as a function of the preparation conditions by measuring film thickness, UV-absorbency, and FT-IR transmittance. The growth rate of the ${\alpha}$-Si:H films increases with increasing substrate temperture, flow rate and R.F. power density. The UV optical band edge shifts to blue with the increases in the deposition pressure. Increasing substrate temperature shifts the UV optical band edge of the films to red. Hydrogen quantity in the ${\alpha}$-Si:H films increases with an increases in the R.F. powr and decreases with an increase in the substrate temperature.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.9-10
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• 2010

Since the discovery of graphene by mechanical exfoliation from graphite[1], various fabrication methods are available today such as chemical exfoliation, epitaxial graphene on SiC substrates, etc. In view of industrialization, the mechanical exfoliation method may not be an option. Epitaxial graphene on SiC substrates, in this respect, is by far more practical because the method consists of conventional thermal treatments familiar to semiconductor industry. Still, the use of the SiC substrate itself, and hence the incompatibility with the Si technology, lessens the importance of this technology in its future industrialization. In this context, we have tackled the problem of forming graphene on Si substrates (GOS). Our strategy is to form an ultrathin (~80 nm) SiC layer on top of a Si substrate, and to graphitize the top SiC layers by a vacuum annealing. We have actually succeeded in forming the GOS structure [2,3,4]. Raman-scattering microscopy indicates presence of few-layer graphene (FLG) formed on our annealed SiC/Si heterostructure, with the G ($1580\;cm^{-1}$) and the G'($2700\;cm^{-1}$) bands, both related to ideal graphene, clearly observed. Presence of the D ($1350\;cm^{-1}$) band indicates presence of defects in our GOS films, whose elimination remains as a challenge in the future. To obtain qualified graphene films on Si substrate, formation of qualified SiC films is crucial in the first place, and is achieved by tuning the growth parameters into a process window[5]. With a potential for forming graphene films on large-scale Si wafers, GOS is a powerful candidate as a key technology in bringing graphene into silicon technology.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.7 no.2
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• pp.197-206
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• 1997

A SiC epilayer on the 6H-SiC crystal substrate was grown by chemical vapor deposition (CVD). The crystal structure of the SiC epilayer was investigated by using the X-ray diffraction patterns and the Roman scattering spectroscopy. The SiC epilayer on the 6H-SiC substrate was grown to be homoepilayer by CVD. In order to distinguish a certain SiC polytype mixed in the SiC crystal grown by the modified Lely method, we have calculated the X-ray diffraction intensities and Brags angles of the typical SiC crystal powders. By comparing the measured X-ray diffraction pattern with the calculated ones, it was identified that the SiC crystal grown by the modified Lely method was the 6H-SiC crystal mixed some 15R-SiC.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.1
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• pp.63-70
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• 2023

Today, the importance of power semiconductors continues to increase due to serious environmental pollution and the importance of energy. Particularly, SiC-MOSFET, which is one of the wide bandgap (WBG) devices, has excellent high voltage characteristics and is very important. However, since the electrical properties of SiC-MOSFET are heatsensitive, thermal management through a package is necessary. In this paper, we propose an insulated metal substrate (IMS) method rather than a direct bonded copper (DBC) substrate method used in conventional power semiconductors. IMS is easier to process than DBC and has a high coefficient of thermal expansion (CTE), which is excellent in terms of cost and reliability. Although the thermal conductivity of the dielectric film, which is an insulating layer of IMS, is low, the low thermal conductivity can be sufficiently overcome by allowing a process to be very thin. Electric-thermal co-simulation was carried out in this study to confirm this, and DBC substrate and IMS were manufactured and experimented for verification.

• Journal of the Korean Vacuum Society
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• v.7 no.1
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• pp.17-23
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• 1998

$Pb(Fe_{0.5}Nb_{0.5}O_3(PFN)$ thin films were prepared by rf magnetron co-sputtering method on $SiO_2/Si$, ITO/glass, and $Pt/Ti/SiO_2/Si$ substrates and post-annealed at the $N_2$ atmosphere by RTA(rapid thermal annerling). The degree of crystallinity of PFN films was identified on various substrates. Electrical properties of PFN films was characterized for $Pt/PFN/Pt/Ti/SiO_2/Si$ structure. The composition of PFN films was estimated by EPMA (electron probe micro analysis). PFN films would be crystallized better to perovskite phase on ITO/glass substrate than $SiO_2/Si$ substrate. This may be induced by the deformation of Pb deficient pyrochlore phase due to Pb diffusion into $SiO_2/Si$ substrate. PFN films on $Pt/Ti/SiO_2/Si$ substrate. PFN films with 5-10% Pb excess were crystallized to perovskite phase from $500^{\circ}C$ temperature. In summary, we show that Pb composition and annealing temperature were critically influenced on crystallinity to perovskite phase. When PFN film with 17% Pb excess was annealed at $600^{\circ}C$ at the $N_2$ atmosphere for 300kV/cm and 88. Its remnant polarization coercive field $2.0 MC/cm^2$ and 144kV/cm, respectively.

• Journal of the Korean Ceramic Society
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• v.34 no.8
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• pp.825-833
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• 1997

Silicon carbide films were deposited by low pressure chemical vapor deposition(LPCVD) using MTS(CH3SICl3) in hydrogen atmosphere on (100) Si substrate. To prevent the unstable interface from being formed on the substrate, the experiments were performed through three deposition processes which were the deposition on 1) as received Si, 2) low temperature grown SiC, and 3) carbonized Si by C2H2. The microstructure of the interface between Si substrates and SiC films was observed by SEM and the adhesion between Si substrates and SiC films was measured through scratch test. The SiC films deposited on the low temperature grown SiC thin films, showed the stable interfacial structures. The interface of the SiC films deposited on carbonized Si, however, was more stable and showed better adhesion than the others. In the case of the low temperature growth process, the optimum condition was 120$0^{\circ}C$ on carbonized Si by 3% C2H2, at 105$0^{\circ}C$, 5 torr, 10 min, showed the most stable interface. As a result of XRD analysis, it was observed that the preferred orientation of (200) plane was increased with Si carbonization. On the basis of the experimental results, the models of defect formation in the process of each deposition were compared.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1879-1881
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• 1999

(Ba,Sr)$TiO_3$[BST] thin films were fabricated on Pt/Ti/$SiO_2$/Si substrate by RF sputtering. We investigated the effects of substrate temperature on the structural and dielectric properties of BST thin films. Increasing the substrate temperature, barium multi titanate phases were decreased, and BST (100), (200) peaks were increased. The relative dielectric constant and dielectric loss of the BST thin films at the substrate temperature of $500^{\circ}C$ were 300 and 0.018, respectively at l[kHz]. In all films, the dielectric constants decreased. Dielectric losses increased as increasing the frequency. The switching voltage was 5V of the BST thin films at the substrate temperature of $500^{\circ}C$.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.10
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• pp.505-509
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• 2004

The (Sr/sub 0.9/Ca/sub 0.1/)TiO₃(SCT) thin films are deposited on Pt-coated electrode(Pt/TiN/SiO₂/Si) using RF sputtering method at various substrate temperature. The optimum conditions of RF power and Ar/O₂ ratio were 140[W] and 80/20, respectively. Deposition rate of SCT thin film was about 18.75[Å/min]. The crystallinity of SCT thin films were increased with increase of substrate temperature in the temperature range of 100～500[℃]. The dielectric constant of SCT thin films were increased with the increase of substrate temperature, and changed almost linearly in temperature ranges of -80～+90[℃]. The current-voltage characteristics of SCT thin films showed the increasing leakage current as the substrate temperature increases.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1998.06a
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• pp.49-54
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• 1998

The growth of diamond films in plasma enhanced chemical vapor deposition(PECVD) processes requires high substrate temperatures and gas pressures, as well as high-power excitation of the gas source. Thus determining the substrate temperature in this severe environment is a challenge. The issue is a critical one since substrate temperature is a key parameter for understanding and optimizing diamond film growth. The precise Si substrate temperature calibration based on rapid-scanning spectroscopic ellipsometry have been developed and utilized. Using the true temperature of the top 200 ${\AA}$ of the Si substrate under diamond growth conditions, real time spectroellipsometry (RTSE) has been performed during the nucleation and growth of nanocrystallind thin films prepared by PECVD. RTSE shows that a significant volume fraction of nondiamond(or{{{{ {sp }^{2 } -bonded}}}}) carbon forms during thin film coalescence and is trapped near the substrate interface between ∼300 ${\AA}$ diamond nuclei.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.257-260
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• 2007

Hydrogenated amorphous silicon thin film transistors were fabricated on a flexible metal substrate. A negative voltage at a floated gate can be induced by a negative substrate bias through a capacitor between the substrate and gate electrode. This can recover the shifted-threshold voltage to an original value.