• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.126-132
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• 1995

The electrical stress of short channel polycrystalline silicon (poly-Si) thin film transistor (TFT) has been investigated. The device characteristics of short channel poly-Si TFT with 5$\mu$m channel length has been observed to be significantly degraded such as a large shift in threshold voltage and asymmetric phenomena after the electrical stress. The dominant degradation mechanism in long channel poly-Si TFT's with 10$\mu$m and 20$\mu$m channel length respectively is charage trappling in gate oxide while that in short channel device with 5.mu.m channel length is defect creation in active poly-Si layer. We propose that the increased defect density within depletion region near drain junction due to high electric field which could be evidenced by kink effect, constitutes the important reason for this significant degradation in short channel poly-Si TFT. The proposed model is verified by comparing the amounts of the defect creation and the charge trapping from the strechout voltage.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1189-1192
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• 2009

Short channel a-Si:H TFT devices with Cu electrodes have been investigated. Short channel TFTs are defined by new plasma etch process. When the channel length becomes shorter, the TFT characteristics (threshold voltage, off current, sub threshold voltage, etc.,) are degraded. These degraded characteristics can be improved through the hydrogen plasma treatment and new gate insulator structure. Using these processes, 15.0 inch XGA LCD panel was fabricated successfully where the channel length of the TFT devices was about 2.5 micrometers.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.239-242
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• 2008

We have investigated the reliability of short channel ($L=1.5{\mu}m$) p-type ELA poly-Si TFTs under hot carrier stress. Threshold voltage of short channel TFT was significantly more shifted to positive direction than that of long channel TFT under the same stress. This result may be attributed to electron trapping at the interface between poly-Si film and gate oxide layer.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.68-74
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• 1998

Improved performance and suppressed short-channel effects of polysilicon thin film transistors (poly-Si TFTs) with very thin electron cyclotron resonance (ECR) $N_2$O-plasma gate oxide have been investigated. Poly-Si TFTs with ECR $N_2$O-plasma oxide ($N_2$O-TFTs) show better performance as well as suppressed short-channel effects than those with conventional thermal oxide. The fabricated $N_2$O-TFTs do not show threshold voltage reduction until the gate length is reduced to 3 ${\mu}{\textrm}{m}$ for n-channel and 1 ${\mu}{\textrm}{m}$ for p-channel, respectively. The improvements are due to the smooth interface, passivation effects, and strong Si ≡ N bonds.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1301-1304
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• 2007

We have investigated degradation of short channel n-type poly-Si TFTs with LDD under high gate and drain voltage stress due to self-heating. We have found that the threshold voltage of short channel TFT is shifted to negative direction on the selfheating stress, whereas the threshold voltage of long channel is moved to positive direction.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1442-1444
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• 1994

The short channel poly-Si TFT is important in aspect of transistor characteristics, packing density and aperture ratio. In this paper, we have reported the degradation phenomena of short channel poly-Si TFT's which had significantly degraded device parameters, such as threshold voltage shift and a great asymmetric degradation, due to gate and drain electrical stress. The reduced effective channel length and expanded depletion region may be the main reason of these significant device parameters.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.867-869
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• 2008

We have investigated the effects of hydrogen plasma treatment by PECVD (Plasma Enhanced Chemical Vapor Deposition) in the back channel region, the method for reducing the off state leakage current which increases with the short channel length of a-Si:H TFTs. To improve the off current characteristics, we analyzed the hydrogen plasma treatment with various RF power and plasma treatment times of PECVD. As the result of hydrogen plasma treatment in the back channel region it was remarkably reduced the off current level of 2um channel length TFT.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1673-1676
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• 2007

We have investigated the degradation mechanism of hydrogenated amorphous silicon (a- Si:H) thin film transistors (TFTs) The threshold voltage of driving a-Si:H TFT is shifted severely by electrical bias due to a charge trapping and defect state creation. And the short channel TFTs exhibit less threshold voltage degradation than long channel TFTs. We propose the pixel circuits employing negative bias annealing scheme in order to suppression of threshold voltage shift of a-Si:H TFT.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.258-260
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• 2008

Developed halftone exposure technique was successfully applied to the fabrication of narrow transistor channels below $4\;{\mu}m$ with conventional photolithography method. Asymmetric slits concept of photo mask was applied to make channel lengths (L) shorter for thin film transistor's (TFT) high performance. These short channel TFTs verified better quality transistor characteristics.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.971-973
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• 1999

채널길이에 따른 n-채널과 p-채널 poly-Si TFT's를 제작하고 그 전기적 특성을 분석하였다. n-채널과 p-채널소자는 공통적으로 기생바이폴라트 랜지스터현상(parasitic bipolar transistor action)에 의한 kink 효과, 전하공유(charge sharing)에 의한 문턱전압의 감소, 소오스와 드레인 근처의 결함에 의한 RSCE(reverse short channel effect) 효과, 수직전계에 의한 이동도의 감소, 그리고 avalanche 증식에 의한 S-swing의 감소가 나타났다. n-채널은 p-채널 보다 더 큰 kink, 이동도, S-swing의 변화가 나타났으며, 높은 드레인 전압에서의 문턱전압의 이동은 avalanche 증식(multiplication)에 의한 것이 더 우세한 것으로 나타났다. 누설전류의 경우, 채널 길이가 짧아짐에 따라 n-채널은 큰 증가를 나타냈으나 p-채널의 경우는 변화가 나타나지 않았다.