• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.37 no.2
• /
• pp.75-82
• /
• 2000

In this Paper, a new type of feedforward linearizer using a delay line which controls the phase characteristics of the correction amplifier block is proposed. The extra delay line provides the control-ability of IM signals so that the IM rejection is accomplished without the conventional pilot tone. The error signal loop consists of several key components such as phase shifter and attenuator, subtractor. These key components are replaced by new designs in order to obtain better linearization characteristics without the pilot tone generator which is indispensable in the conventional linearizer designs. The proposed linearizer was designed at Korean PCS band and combined with 35W HPA manufactured by KMW inc., and tested with two-tone signals separated 0.6MHz apart at the center frequency of 1855MHz. The experimental results show C/l improvement by 16.9 ~ 24.6 dB over 15 dB dynamic range(30 ~45 dBm) which gave IMD of 58.5~63.2 dBc for the designed LPA.

• Journal of the Earthquake Engineering Society of Korea
• /
• v.11 no.1 s.53
• /
• pp.21-27
• /
• 2007

In this study, an approach that installs seismic isolation bearings was proposed for the seismic retrofit of the existing bridges. The method that replaces all existing bearings with seismic isolators was proposed already. However, in this study, we recommend to utilize the existing bearings for the benefit of safety and cost. According to our proposal, the seismic isolators do not support vertical loads but they Just function as the period shifter and the horizontal damper. To verify this approach experimentally, the real scale bearings and lead rubber bearings far the real highway bridges were designed and fabricated. And the responses of this isolated bridges to the assumed earthquakes were determined by the pseudo dynamic test scheme. The test results were also compared to the responses computed by the well known structural analysis software to check the reliability of the test. From the test results, we found that the retrofitted bridges using the proposed method showed stable performances under earthquakes.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.11
• /
• pp.123-130
• /
• 2004

This paper describes a multiplier architecture optimized for 32 bit RISC processor with 3-stage pipeline. The multiplier of ARM7, the target processor, is variably carried out on the execution stage of pipeline within 7 cycles. The included multiplier employs a modified Booth's algerian to produce 64 bit multiplication and addition product and it has 6 separate instructions. We analyzed several multiplication algorithm such as radix4-32${\times}$8, radix4-32${\times}$16 and radix8-32${\times}$32 to decide which multiplication architecture is most fit for a typical architecture of ARM7. VLSI area, cycle delay time and execution cycle number is the index of an efficient design and the final multiplier was designed on these indexes. To verify the operation of embedded multiplier, it was simulated with various audio algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.3 s.357
• /
• pp.26-34
• /
• 2007

This Paper describes a chip design technique for body composition analyzer based on the BIA (Bioelectrical Impedance Analysis) method. All the functions of signal forcing circuits to the body, signal detecting circuits from the body, Micom, SRAM and EEPROMS are integrated in one chip. Especially, multi-frequency detecting method can be applied with selective band pass filter (BPF), which is designed in weak inversion region for low power consumption. In addition new full wave rectifier (FWR) is also proposed with differential difference amplifier (DDA) for high performance (small die area low power consumption, rail-to-rail output swing). The prototype chip is implemented with 0.35um CMOS technology and shows the power dissipation of 6 mW at the supply voltage of 3.3V. The die area of prototype chip is $5mm\times5mm$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.2
• /
• pp.110-120
• /
• 2010

In this paper, we propose a tunable SIW(Substrate Integrated Waveguide) using dielectric screws for eliminating the phase imbalance of large size power distribution networks(PDN). Alumina screws partially inserted into several through holes of the tunable SIW section effectively change the phase shift without S-parameter degradation. ${\pm}33.9^{\circ}$ measured phase imbalance of a large conventional 9 GHz SIW-PDN of $370\;mm{\times}195\;mm$ size has been greatly reduced to ${\pm}4.65^{\circ}$. We expect that the proposed tunable SIW plays an important role for a light-weight, high performance substrate integrated phased array system(Si-PAS) and large size SIW circuit applications.

• Journal of Ocean Engineering and Technology
• /
• v.24 no.1
• /
• pp.166-171
• /
• 2010

In this paper, the front-end of a digital receiver with a 25 kHz carrier frequency, 5 kHz symbol rate, and any excess-bandwidth is designed using two basic facts. The first is known as the uniform sampling theorem, which states that the sampled sequence might not suffer from aliasing even if its sampling rate is lower than the Nyquist sampling rate if the analog signal is a bandpass one. The other fact is that if the sampling rate is 4 times the center frequency of the sampled sequence, the front-end processing complexity can be dramatically reduced due to the half of the sampled sequence to be multiplied by zero in the demixing process. Furthermore, the designed front-end is simplified by introducing sub-filters and sub-sampling sequences. The designed front-end is composed of an A/D converter, which takes samples of a bandpass filtered signal at a 20 kHz rate; a serial-to-parallel converter, which converts a sampled bandpass sequence to 4 parallel sub-sample sequences; 4 sub-filter blocks, which act as a frequency shifter and lowpass filter for a complex sequence; 4 synchronized switches; and 2 adders. The designed front-end dramatically reduces the computational complexity by more than 50% for frequency shifting and lowpass filtering operations since a conventional front-end requires a frequency shifting and two lowpass filtering operations to get one lowpass complex sample, while the proposed front-end requires only four filtering operation to get four lowpass complex samples, which is equivalent to one filtering operation for one sample.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.26 no.5
• /
• pp.521-524
• /
• 2015

This letter presents a selective wireless power transfer architecture using a reconfigurable multi-port amplifier. The proposed wireless power transfer architecture is composed of a phase shifter part controlled by FPGA, two class-E power amplifiers, a four-port power combiner and two coil loads. Depending on the phase control of FPGA, the power ratio of outputs at the two coil loads becomes 1:1, 2:0 and 0:2. The manufactured system has delivered 1W DC power to loads at 125 kHz. The total DC-to-DC conversion efficiency shows more than 40 % including PA efficiency of 79 %.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.12
• /
• pp.3205-3214
• /
• 1996

In this paper, the microstrip phased array antennas with coupling-slots for the base station of mobile communication is proposed and anlyzed with accurate analysis method which is based on both reciprocity principle and full-wave analysis. The basis functions used for the numerical analysis are determined depending upon the accuracy, convergence properties of the solution, and the computation time. The patch uses 3 EB mode and the slot uses IPWS mode. The designed phased array antenna has 8 slot-coupled microstrip patch array elements and the beam scanning capability is obtained by using the 4-bit PIN-diode phase shifters as switching devices which are consisted of the loaded line phase shifters for 30.deg. and 60.deg. and the reflection type phase shifters for 90.deg. and 180.deg. repectively. The 4-bits phase shifters which aremade by connecting each phase shifter have about 2.deg.-3.deg. phase errors and their insertion loss are about 3dB for each phase state. The fabricated 8-element phased array antenna with 4-bits phase shifters provides 12.deg.-14.deg. beamwidths depending on the scanning angle and is capable of scanning its beam to .+-.45.deg. with 9.deg. intervals, and the gain 12dBi. The overall results show that the slot-coupled phased array antenna has great advantages of wideband, high gain and reduced spurious radiation. Also, the antenna can be made small and thin. Furthermore, the scanning property of this antenna allows for its application in several areas, such as mobile communication system and PCS.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.23 no.5
• /
• pp.388-396
• /
• 2010

In this study, we propose characteristics improvement methods according to via hole plating method for FBAR Duplexer with bandwidth($T_x4: 1850 MHz ~ 1910 MHz, $R_x$:1930 MHz ~ 1990 MHz) which is used for wireless systems. Also, we designed and fabricated $3.8{\times}3.8{\times}1.8mm$ size microminiature FBAR Duplexer based on this proposal. First of all, in this study, we fabricated pentagon shape resonators by different size to make filter combination, and their quality factor(Q) are 687 with 6.6% of ${k_{eff}}^2$. Using this resonators, we designed $3{\times}2$ Type $T_x$ filter and $3{\times}4$ Type $R_x$ filter. The transmission line, which works as phase shifter, is designed with 210 ${\mu}m$ in width and 18 mm in length Stripline type. Inductor, which is used for matching component, is designed with width of 75 ${\mu}m$, a technically achievable minimum width. And adopted plating method of filling via hole with conductive epoxy for improved grounding and thermal conductivity. Using these configuration with all of the matching component values, we found Duplexer characteristics of -1.57 dB ~ -1.73 dB in insertion loss, -56 dB in attenuation at 1850 MHz ~ 1910 MHz of $T_x$ band. Also, found -2.71 dB ~ -3.23 dB in insertion loss, -58 dB in attenuation at 1930 MHz ~ 1990 MHz of $R_x$ band.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.42 no.1
• /
• pp.111-118
• /
• 2005

The shape of vertical pattern of base station antenna affects greatly quality of the communication of not only a service zone but also adjacent cells and then it is an important point to be considered in designing cell coverage. Currently type of vertical patterns to be applied to base station antenna are divided into five classes. In designing antenna, these five classes are applied solely or compositely according to the environment to be used antenna. In this paper, the dual polarized antenna for base station that is with a continuous electrical down tilting and with a shaped beam pattern, that an upper side lobe is suppressed and a lower null is filled, is designed and fabricated for synthesizing of the shape beant the pattern synthesis methods proposed by R. S. Elliott is used sequentially and for the electrical don tilting, the phased array theory is applied. Measured results show the down tilting range from 0° to 14°, the gain of Min. 13.3dBi and the upper side lobe of Max. -23dB. And we verified that upper side lobe is not to vary greatly and null filling performance is favorable overall.