• ETRI Journal
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• 제43권5호
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• pp.900-908
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• 2021

This paper proposes thermometer-code latches having five and six transistors for unidirectional and bidirectional thermometer-code shift-registers, respectively. The proposed latches omit the set and reset transistors by changing from two supply voltage nodes to the set and reset signals in the cross-coupled inverter. They set or reset the data by changing the supply voltage to ground in either of two inverters. They reduce the number of transistors to five and six compared with the conventional thermometer-code latches having six and eight transistors, respectively. The proposed thermometer-code latches were simulated using a 65 nm complementary metal-oxide-semiconductor (CMOS) process. For comparison, the proposed and conventional latches are adapted to the 64 bit thermometer-code shift-registers. The proposed unidirectional and bidirectional shift-registers occupy 140 ㎛² and 197 ㎛², respectively. Their consumption powers are 4.6 ㎼ and 5.3 ㎼ at a 100 MHz clock frequency with the supply voltage of 1.2 V. They decrease the areas by 16% and 13% compared with the conventional thermometer-code shift-register.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 1999년도 High Temperature Superconductivity Vol.IX
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• pp.102-106
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• 1999

We have designed and fabricated a four-bit shift register circuit using YBCO bicrystal junctions and experimentally tested its operations by a computer-controlled digital measurement set-up. Laser ablated YBCO thin films with clean surface were used in this work. The circuit consists of the shift register and two read SQUIDs placed next to each sides of the shift register. The SQUIDs were inductively coupled to the nearby shift register stages. A probe equipped with high speed coax lines were used in this experiment. The major obstacle in testing the circuit was the interference between the read SQUIDs and we solved the problem by finding the correct operation points of the SQUIDs from the simultaneously measured modulation curves. Loaded Data("1" or "0") were successfully shifted from a stage to the next one by a controlled current pulse injected to the bias lines located between the stages and the data shifts were correctly monitored by the read SQUIDs

• ETRI Journal
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• 제36권2호
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• pp.321-324
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• 2014

This letter describes a two-phase clock oxide thin-film transistor shift register that executes a robust operation over a wide threshold voltage range and clock coupling noises. The proposed circuit employs an additional Q generation block to avoid the clock coupling noise effects. A SMART-SPICE simulation shows that the stable shift register operation is established for the clock coupling noises and the threshold voltage variation from -4 V to 5 V at a line time of $5{\mu}s$. The magnitude of coupling noises on the Q(15) node and Qb(15) node of the 15th stage is respectively -12.6 dB and -26.1 dB at 100 kHz in the proposed circuit, compared to 6.8 dB and 10.9 dB in a conventional one. In addition, the estimated power consumption is 1.74 mW for the proposed 16-stage shift registers at $V_{TH}=-1.56V$, compared to 11.5 mW for the conventional circuits.

• Progress in Superconductivity
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• 제1권1호
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• pp.31-35
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• 1999

We have fabricated and tested a simple circuit of the rapid single-flux-quantum(RSFQ) four-stage shift register using a single layer high-$T_c$ superconducting (HTS) $YBa_2Cu_3O_{7-x}$ (YBCO) thin film structure with 9 step-edge Josephson junctions. The circuit includes two read superconducting quantum interference devices(SQUID) and four stages. To establish a robust HTS RSFQ device fabrication process, we have focussed on the reproducible process of sharp and straight step-edge formation as well as the ratio of film thickness to step height, t/h. The spread of step-edge junction parameters was measured from each 13 junctions with t/h=1/3, 1/2, and 2/3 at various temperatures. We have demonstrated the simplified operation of the shift register at 65 K.

• 한국통신학회논문지
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• 제18권1호
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• pp.83-91
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• 1993

디지틀 전송 시스팀에서 순방향 에러 제어(Forward Error Control) 방식으로 에러를 검출할 수 있는 성능과 구현의 용이함에 의해 Cyclic Redundancy Chedk(CRC) code가 널리 사용도고 있다. 즉, 간단한 몇개의 shift register와 modulo2 가산기를 이용하여 회로를 구성하고 입력 데이터 열을 직렬로 입력하면 최종적으로 shift register에 남아 있는 값이 CRC code가 되어 입력 데이터 열을 전송한 뒤 shift register의 값들을 순차적으로 전송하는 방식으로 전성 사의 에러를 검출하고 수정한다. 그러나 전송속도가 높아짐에 따라 직렬 데이터를 이용하여 CRC code를 생성하는 회로를 구현하는 것은 반도체 소자의 속도 제약 때문에 많은 어려움이 따른다. 따라서 본 논문에서는 주문형 반도체 개발시 반도체 소자의 속도 제약 문제를 해소하기 위하여 입력데이터 열을 병렬로 입력하여 직렬로 수행하는 방식과 동일한 방식으로 동작하는 병렬 CRC code 생성방식 및 syndrome 계산방식을 제안하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.2269-2270
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• 2008

Zigbee that is the wireless personal area networks communication technology for low power consumption is low-cost, low-power consumption, and small size and program code. From the present paper symbol and chip sequence of existing Zigbee module undergarment PN code generators which are a 1:1 mapping method it uses shift register and it plans the method which it proposes. The experimental result used Xilinx ISE and it measured synthesis and timing and power.

• Journal of applied mathematics & informatics
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• 제39권5_6호
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• pp.859-882
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• 2021

In the proposed paper, a new algorithm based on Nonlinear Feedback Shift Register (NLFSR) and modified RC4A (Rivest Cipher 4A) cipher is introduced. NLFSR is used for image pixel scrambling while modified RC4A algorithm is used for pixel substitution. NLFSR used in this algorithm is of order 27 with maximum period 2^27-1 which was found using Field Programmable Gate Arrays (FPGA), a searching method. Modified RC4A algorithm is the modification of RC4A and is modified by introducing non-linear rotation operator in the Key Scheduling Algorithm (KSA) of RC4A cipher. Analysis of occlusion attack (up to 62.5% pixels), noise (salt and pepper, Poisson) attack and key sensitivity are performed to assess the concreteness of the proposed method. Also, some statistical and security analyses are evaluated on various images of different size to empirically assess the robustness of the proposed scheme.

• 한국통신학회논문지
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• 제14권3호
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• pp.235-239
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• 1989

유한체 GF($2^m$)상에서 임의의 두 원소를 곱하는 승산기를 제시하였으며 동작과정을 단계별로 설명하였다. 본 논문에서 제시된 회로는 기준의 선형궤한 치환 레지스터를 이용한 회로가 변형된 형태로서 m단 궤환치환 레지스터, m-1개의 플립플롭, m개의 AND게이트, 그리고 m-입력 XOR 게이트로 구성되며 회로가 간단하다. GF($2^m$)의 두 원소를 곱할 때, 기존의 치환 레시스터 승산기는 m번 치환하면 곱셈의 결과가 레지스터에 축적되므로 m클럭시간 만큼 지연되는 반면 제안된 승산기는 입력되고부터 직렬출력을 얻을 때까지 m-1 클럭시간이 소요되며 cellular-array 승산기에 비해 매우 간단하고 systolic 승산기에 비해서는 지연시간도 단축된다.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2001년도 High Temperature Superconductivity Vol.XI
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• pp.48-48
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• 2001

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.411-415
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• 1987

A $32{\times}33$ MOS-type area image sensor has been fabricated. The blooming current is reduced to 1/14 by forming +p photocell in P-well instead of a simple p-type substrate. A shallow n+ junction is made to improve the sensitivity of photodiode on short wavelength. Bootstrapping circuit technique is applied to obtain high speed dynamic shift register. The shift register operates at up to 10MHz for 7V clock.