• Title/Summary/Keyword: Serial divider

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Hardware Implementation of Minimized Serial-Divider for Image Frame-Unit Processing in Mobile Phone Camera. (Mobile Phone Camera의 이미지 프레임 단위 처리를 위한 소형화된 Serial-Divider의 하드웨어 구현)

  • Kim, Kyung-Rin;Lee, Sung-Jin;Kim, Hyun-Soo;Kim, Kang-Joo;Kang, Bong-Soon
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2007.10a
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    • pp.119-122
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    • 2007
  • In this paper, we propose the method of hardware-design for the division operation of image frame-unit processing in mobile phone camera. Generally, there are two types of the data processing, which are the parallel and serial type. The parallel type makes it possible to process in realtime, but it needs significant hardware size due to many comparators and buffer memories. Compare the serial type with the parallel type, the hardware size of the serial type is smaller than the other because it uses only one comparator, but serial type is not able to process in realtime. To use the hardware resources efficiently, we employ the serial divider since frame-unit operation for image processing does not need realtime process. When compared with both in the same bit size and operating frequency, the hardware size of the serial divider is approximately in the ratio of 13 percentage compared with the parallel divider.

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Design of a New Bit-serial Multiplier/Divier Architecture (새로운 Bit-serial 방식의 곱셈기 및 나눗셈기 아키텍쳐 설계)

  • 옹수환;선우명훈
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.3
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    • pp.17-25
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    • 1999
  • This paper proposes a new bit-serial multiplier/divider architecture to reduce the hardware complexity significantly and to maintain the same number of cycles compared with existing architectures. Since the proposed bit-serial multiplier/divider architecture does not extend the number of bits in registers and an adde $r_tractor to calculate a partial product or a partial remainder, the hardware overhead can be greatly reduced. In addition, the proposed architecture can perform an additio $n_traction and a shift operation in parallel and the number of cycles for $\textit{N}$-bit multiplication and division for the proposed circuits is $\textit{N}$ and $\textit{N}$ + 2, repectively. Thus, the number of cycles for multiplication and division is the same compared with existing architectures. The SliM Image Processor employs the proposed multiplier/divider architecture and proves the performance of the proposed architecture.cture.

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Efficient systolic VLSI architecture for division in $GF(2^m)$ ($GF(2^m)$ 상에서의 나눗셈연산을 위한 효율적인 시스톨릭 VLSI 구조)

  • Kim, Ju-Young;Park, Tae-Geun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.3 s.357
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    • pp.35-42
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    • 2007
  • The finite-field division can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field division takes much time to compute. In this paper, we propose a radix-4 systolic divider on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed divide, is mathematically developed and new counter structure is proposed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for YLSI design. Compared to the bit-parallel, bit-serial and digit-serial dividers, the proposed divider has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field divider using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

Design of a Bit-Serial Divider in GF(2$^{m}$ ) for Elliptic Curve Cryptosystem (타원곡선 암호시스템을 위한 GF(2$^{m}$ )상의 비트-시리얼 나눗셈기 설계)

  • 김창훈;홍춘표;김남식;권순학
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.12C
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    • pp.1288-1298
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    • 2002
  • To implement elliptic curve cryptosystem in GF(2$\^$m/) at high speed, a fast divider is required. Although bit-parallel architecture is well suited for high speed division operations, elliptic curve cryptosystem requires large m(at least 163) to support a sufficient security. In other words, since the bit-parallel architecture has an area complexity of 0(m$\^$m/), it is not suited for this application. In this paper, we propose a new serial-in serial-out systolic array for computing division operations in GF(2$\^$m/) using the standard basis representation. Based on a modified version of tile binary extended greatest common divisor algorithm, we obtain a new data dependence graph and design an efficient bit-serial systolic divider. The proposed divider has 0(m) time complexity and 0(m) area complexity. If input data come in continuously, the proposed divider can produce division results at a rate of one per m clock cycles, after an initial delay of 5m-2 cycles. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. Since the proposed divider can perform division operations at high speed with the reduced chip area, it is well suited for division circuit of elliptic curve cryptosystem. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomial, and has a unidirectional data flow and regularity, it provides a high flexibility and scalability with respect to the field size m.

1.8-GHz Six-Port-Based Impedance Modulator Using CMOS Technology (CMOS 공정을 이용한 1.8 GHz 6-포트 기반의 임피던스 변조기)

  • Kim, Jinhyun;Kim, Jeong-Geun
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.29 no.5
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    • pp.383-388
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    • 2018
  • This paper presents a 1.8 GHz six-port-based impedance modulator using CMOS technology, which can select an arbitrary load impedance with switch control. The proposed 1.8-GHz impedance modulator comprises a Wilkinson power divider, three quadrature hybrid couplers, and four SP3T switches for each load impedance selection. The measured insertion loss of -13 dB and the input/output return losses of >10 dB are achieved in the range of 1.4~2.2 GHz. The low drop output regulator for a stable 3.3 V DC power and the serial peripheral interface(SPI) for an easy digital control are integrated. The chip size, including the pads, is $1.7{\times}1.8mm^2$.

Design of Variable Average Operation without the Divider for Various Image Sizes (다양한 영상크기에 적합한 나눗셈기를 사용하지 않은 가변적 평균기의 설계)

  • Yang, Jeong-Ju;Jeong, Hyo-Won;Lee, Sung-Mok;Choi, Won-Tae;Kang, Bong-Soon
    • Journal of the Institute of Convergence Signal Processing
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    • v.10 no.4
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    • pp.267-273
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    • 2009
  • In this paper, we proposed a variable average operation for a WDR(Wide Dynamic Range). The previously proposed average operation [5] improves hardware efficiency and complexity by replacing divider with multiplier. However, the previously proposed method has some weak-points. For example, there are counting horizontal and vertical length, and then the multiplier selects a Mode set by the user when the lengths exactly correspond with the image's size in the Mode. To compensate some weak-points, we change a Mode selection methods as a using the image's total size. Also, we propose another feature that it can be applied to various image sizes. To get a more accurate average, we add an external compensation value. We design the variable average operation using a Verilog-HDL and confirm that the Serial Multiplier's structure is better efficiency than Split Multiplier's structure.

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A Real time Image Resizer with Enhanced Scaling Precision and Self Parameter Calculation (강화된 스케일링 정밀도와 자체 파라미터 계산 기능을 가진 실시간 이미지 크기 조절기)

  • Kim, Kihyun;Ryoo, Kwangki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.99-102
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    • 2012
  • An image scaler is a IP used in a image processing block of display devices to adjust image size. Proposed image scaler adopts line memories instead of a conventional method using a frame memory. This method reduced hardware resources and enhanced data precision by using shift operations that number is multiplied by $2^m$ and divided again at final stage for scaling. Also image scaler increased efficiency of IP by using serial divider to calculate parameters by itself. Parameters used in image scaling is automatically produced by it. Suggested methods are designed by Verilog HDL and implemented with Xilinx Vertex-4 XC4LX80 and ASIC using TSMC 0.18um process.

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Design of Fast Elliptic Curve Crypto module for Mobile Hand Communication

  • Kim, Jung-Tae
    • Journal of information and communication convergence engineering
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    • v.6 no.2
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    • pp.177-181
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    • 2008
  • The more improved the Internet and the information technology, the stronger cryptographic system is required which can satisfy the information security on the platform of personal hand-held devices or smart card system. This paper introduces a case study of designing an elliptic curve cryptographic processor of a high performance that can be suitably used in a wireless communicating device or in an embedded system. To design an efficient cryptographic system, we first analyzed the operation hierarchy of the elliptic curve cryptographic system and then implemented the system by adopting a serial cell multiplier and modified Euclid divider. Simulation result shows that the system was correctly designed and it can compute thousands of operations per a second. The operating frequency used in simulation is about 66MHz and gate counts are approximately 229,284.

Design of ECC Scalar Multiplier based on a new Finite Field Division Algorithm (새로운 유한체 나눗셈기를 이용한 타원곡선암호(ECC) 스칼라 곱셈기의 설계)

  • 김의석;정용진
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.5C
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    • pp.726-736
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    • 2004
  • In this paper, we proposed a new scalar multiplier structure needed for an elliptic curve cryptosystem(ECC) over the standard basis in GF(2$^{163}$ ). It consists of a bit-serial multiplier and a divider with control logics, and the divider consumes most of the processing time. To speed up the division processing, we developed a new division algorithm based on the extended Euclid algorithm. Dynamic data dependency of the Euclid algorithm has been transformed to static and fixed data flow by a localization technique, to make it independent of the input and field polynomial. Compared to other existing scalar multipliers, the new scalar multiplier requires smaller gate counts with improved processor performance. It has been synthesized using Samsung 0.18 um CMOS technology, and the maximum operating frequency is estimated 250 MHz. The resulting performance is 148 kbps, that is, it takes 1.1 msec to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.

Design of a Elliptic Curve Crypto-Processor for Hand-Held Devices (휴대 단말기용 타원곡선 암호 프로세서의 설계)

  • Lee, Wan-Bok;Kim, Jung-Tae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.4
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    • pp.728-736
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    • 2007
  • The more improved the Internet and the information technology, the stronger cryptographic system is required which can satisfy the information security on the platform of personal hand-held devices or smart card system. This paper introduces a case study of designing an elliptic curve cryptographic processor of a high performance that can be suitably used in a wireless communicating device or in an embedded system. To design an efficient cryptographic system, we first analyzed the operation hierarchy of the elliptic curve cryptographic system and then implemented the system by adopting a serial cell multiplier and modified Euclid divider. Simulation result shows that the system was correctly designed and it can compute thousands of operations per a secdond.