• 전력전자학회논문지
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• 제9권6호
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• pp.620-627
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• 2004

H-브릿지 멀티레벨 인버터는 여러 개의 단상 Power Cell을 직렬로 연결함으로써 저전압 전력용 반도체를 사용하여 고전압을 얻을 수 있고, 정현파에 가까운 출력전압 파형을 얻을 수 있는 멀티레벨 인버터 토폴로지이다. 본 논문은 산업현장에서 신뢰성을 인정받아 많이 사용되고 있는 직렬통신 방식의 일종인 CAN통신 인터럽터를 이용한 H-브릿지 멀티레벨 인버터 Power Cell의 PU 동기화 및 위상전이 방법에 관한 것이다. 제안된 방법의 주요 장점은 주제어기와 셀 제어기 사이에 직렬통신(CAN)을 사용함으로써 주제어기와 셀 제어기의 신호선의 단순화, 주제어기의 부담 감소, Power Cell의 모듈화, 셀 단위의 보호동작 용이, 확장성 향상 그리고 제어 신호 및 Power Cell의 신뢰성을 향상에 있다. 13레벨로 구성된 H-브릿지 멀티레벨 인버터 시험을 통해 제안된 방법의 타당성과 신뢰성을 입증하였다.

• 한국정보통신학회논문지
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• 제8권6호
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• pp.1188-1193
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• 2004

비도 높은 암호용으로 연구된 유한체 곱셈 연산기는 크게 직렬 유한체 곱셈기, 배열 유한체 곱셈기, 하이브리드 유한체 곱셈기으로 분류되어 왔다. 직렬 유한체 곱셈기는 마스트로비토 (Mastrovito) (1)에 의하여 제안되어 유한체 곱셈기의 가장 기본적인 구조로 자리잡아 왔고, 이를 병렬로 처리하기 위해 m 배의 자원을 투자하여 m 배의 속도를 얻어낸 결과가 2차원 배열 유한체 곱셈기이며 (2), 이들 기존 방식의 장점만을 취하여 제안된 방식이 1999년 Paar에 의해 제안된 하이브리드 (hybrid) 곱셈기이다 (3). 반면 이 하이브리드 곱셈기는 사용 가능한 유한체로서 유한체의 차수를 합성수로 사용해야 한다는 제약이 따른다. 본 논문에서는 마스트로비토의 곱셈기의 구조를 기본으로 하고, 수식적으로 공통인수를 끌어내어 후처리하는 기법을 유도하여 적용한다. 제안한 방식으로 설계한 새로운 유한체 곱셈기는 HDL로 구현하여 소프트웨어 측면 뿐 아니라 하드웨어 측면에서도 그 기능과 성능을 검증하였다. 제안된 방식에서 직렬 다항 기준식 (polynomial)을 t (t는 1보다 큰 양의 정수) 부분으로 나누어 적용하였을 경우 곱셈기는 t 배의 속도 향상을 보일 수 있다.

• 전자공학회논문지S
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• 제34S권2호
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• pp.43-51
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• 1997

In this paper, we quantize the image data to simplify the systolic array architecture for block matching algorithm. As the number of bits for pixel data to be processed is reduced by quantization, one can simplify the hardware of systolic array. Especially, if the bit serial input is used, one can even more simplify the structure of processing element. First, we analize the effect of quantization to a block matching. then we show the structure of quantizer and processing element when bit serial input is used. The simulation results applied to standard images have shown that the proposed block matching method has less prediction error than the conventional high speed algorithm.

• 전기학회논문지P
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• 제58권1호
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• pp.27-32
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• 2009

A technical system generally comprise a number of subsystems and components that are interconnected in such a way that the system is able to perform a set of required function. Because of the complex system structure with serial, parallel and bridged connections, some certain subsystems or components are more critical than the others. The main concern of a reliability engineer is to identify potential failures and to prevent these failures from occurring. In order to prevent fatal failures, proper inspections and maintenance actions for each component are required Considering above objectives of reliability engineers and characteristics of a practical system, several practical method for evaluating system and component reliabilities have developed namely Birnbaum's and Fussell & Vesely's measures. However there are several critical weaknesses in traditional calculation process as the target system gets larger. In this paper, a new technique for calculating component's structural importance is proposed and compared to Birnbaum's with representative system examples (serial, parallel. k out of n, and bridge type).

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.118-125
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• 2016

This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.289-292
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• 2002

In this paper, an efficient architecture for the finite field multiplier is proposed. This architecture is faster and smaller than any other LFSR architectures. The traditional LFSR architecture needs t x m registers for achieving the t times speed. But, we designed He multiplier using a novel fast architecture without increasing the number of registers. The proposed multiplier is verified with a VHDL description using SYNOPSYS simulator. The measured results show that the proposed multiplier is 2 times faster than the serial LFSR multiplier. The proposed multiplier is expected to become even more advantageous in the smart card cryptography processors.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제55권7호
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• pp.362-368
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• 2006

This paper presents the results of a small capacitive current interruption test for the three types of interrupter which are called 'serial type', 'parallel/separated type' and 'puffer type' according to the arrangement of the thermal expansion chamber and the puffer cylinder. After the preconditioning test the small current interruption capability of the 'puffer type' decreased, on the contrary, that of the hybrid interrupters increased. A number of reignition have been occurred in the 'serial type' hybrid interrupter and the change of small current interruption capability after preconditioning test is mainly influenced by the structure of interrupter. Finally it has been proved that the 'parallel/separated type' hybrid interrupter has the best interruption performance through the verification tests.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 F
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• pp.2030-2032
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• 1998

It is always necessary to high performance power supplies for the magnet system in the accelerator, especially when the number of power supplies are large. When have developed the compact power supply using switching technology instead of SCR phase control. We adopt the pulse width modulation(PWM) method with a half bridge DC/DC converter. In this way, we can make a compact system with light weight and small volume. Actual system we developed is 1.2kW, 35V/35A bipolar DC power supply current precision of +/-0.02%. It is possible to mount 10 unit in a conventional 19 rack. The built in controller has an RS422 protocol to drive 10 unit by one serial port up to 1.2km distance. If we adopt RS485 protocol, one serial port can control 32 power supplies. In this paper, we will report the design and performance of the prototype power supply.

• Nuclear Engineering and Technology
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• 제53권11호
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• pp.3790-3797
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• 2021

Although the individual channel readout method can improve the performance of PET detectors with pixelated photo-sensors, such as silicon photomultiplier (SiPM), this method leads to a significant increase in the number of readout channels. In this study, we proposed a novel multiplexing method that could effectively reduce the number of readout channels to reduce system complexity and development cost. The proposed multiplexing circuit was designed to generate bipolar pulses with different zero-crossing points by adjusting the time constant of the high-pass filter connected to each channel of a pixelated photo-sensor. The channel position of the detected gamma-ray was identified by estimating the width between the rising edge and the zero-crossing point of the bipolar pulse. In order to evaluate the performance of the proposed multiplexing circuit, four detector blocks, each consisting of a 4 × 4 array of 3 mm × 3 mm × 20 mm LYSO and a 4 × 4 SiPM array, were constructed. The average energy resolution was 13.2 ± 1.1% for all 64 crystal pixels and each pixel position was accurately identified. A coincidence timing resolution was 580 ± 12 ps. The experimental results indicated that the novel multiplexing method proposed in this study is able to effectively reduce the number of readout channels while maintaining accurate position identification with good energy and timing performance. In addition, it could be useful for the development of PET systems consisting of a large number of pixelated detectors.

• Archives of Plastic Surgery
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• 제44권6호
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• pp.523-529
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• 2017

Background Serial tissue expansion is performed to remove giant congenital melanocytic nevi. However, there have been no studies comparing the expansion rate between the subsequent and preceding expansions. In this study, we analyzed the rate of expansion in accordance with the number of surgeries, expander location, expander size, and sex. Methods A retrospective analysis was performed in pediatric patients who underwent tissue expansion for giant congenital melanocytic nevi. We tested four factors that may influence the expansion rate: The number of surgeries, expander location, expander size, and sex. The rate of expansion was calculated by dividing the 'inflation amount' by the 'expander size'. Results The expansion rate, compared with the first-time group, was 1.25 times higher in the second-or-more group (P=0.04) and 1.84 times higher in the third-or-more group (P<0.01). The expansion rate was higher at the trunk than at other sites (P<0.01). There was a tendency of lower expansion rate for larger expanders (P=0.03). Sex did not affect the expansion rate. Conclusions There was a positive correlation between the number of surgeries and the expansion rate, a positive correlation between the expander location and the expansion rate, and a negative correlation between the expander size and the expansion rate.