• Title/Summary/Keyword: Serial I/O

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Implementation of DSP Embeded ASIC for Multimedia Communicatioin (멀티미디어 통신용 Vocoder 갭라용 DSP Embeded ASIC 개발)

  • 성유나
    • Proceedings of the Acoustical Society of Korea Conference
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    • 1998.08a
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    • pp.165-168
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    • 1998
  • 제안하고 있는 CSD17C00 chip은 C&S technology에서 개발한 것으로, 음성 신호 처리를 위해 범용으로 구현되었으며, 16 bit 40 MIPS DSP group OAK DSP Core를 포함, 이에 Miscellaneous Logic, Serial Port, Host Interface, Timer, Compander 의 5가지 Peripherals 과 범용 I/O Ports 로 설계되었다. 1차적으로 CSD17C00 Chip 의 성능을 점검하였다. 그 결과, 응용 프로그램은 28MIPS의 계산속도를 갖으며, 프로그램 ROM 크기는 8.85KWords 이고, 10KWords 의 데이터 ROM 과 4KWords 데이터 RAM을 필요로 한다. CSD17C00 CHIP은 멀티미디어 통신용 VOCODER 개발을 위한 범용성을 갖추고 있으며, VOCODER 용 S/W 개발 환경 및 H/W 구조가 여타 범용 DSP에 비해편의성고 K합리성을 제공하도록 설계되어 있다. 따라서, 이를 이용한다면, 멀티 미디어 통신용 VOCODER, INTERNET PHONE CO-PROCESSOR, DIGITAL RECODER, MPEG AUDIO ENCODER & DECODER 등 다양한 제품으로의 응용이 가능할 것으로 전망된다.

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The Design of Monitor Program for MC68000 Based System (MC68000 시스템을 위한 모니터 프로그램 설계)

  • Lee, B.R.;Chung, C.H.
    • Proceedings of the KIEE Conference
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    • 1993.07a
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    • pp.507-509
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    • 1993
  • The monitor program, which controls overall operation of MC68000 based system and executes some commands and I/O operations, is a system program and consists of functions that executes these operations. Monitor program can be easily applied to design a digital filter. This paper approaches to the object, to which refer above, by considerng algorithm of monitor program, which operates in M68000 based system, and concerning theory. This monitor program operate by the serial communication between host IBM-PC and target MC68000 system with MC6850 and MAX232C.

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An Efficient Lighting Control System Design for LSDM Control on AVR (AVR 기반의 LSDM 제어를 위한 효율적인 점등제어 시스템 설계)

  • Hong, Sung-Il;Lin, Chi-Ho
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.11 no.5
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    • pp.116-124
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    • 2012
  • In this paper, we propose an efficient lighting control system design for AVR based LSDM control. This paper, an efficient lighting control system design for LSDM control be design divided as the signal control part for I/O data bus and the timer/counter part for clock signal control according to operating conditions. LSDM control logic be optimization to PORTx and DDRx register by specifying the logical value of each bit for effective control signal processing. And, the LSDM control signal by lighting control program execution of ATmega128 be designed to be LSDM lighting control by control logic operating. In this paper, a proposed lighting control system were measured to power loss rate to proved the power loss reduction about lighting status of LSDM control logic by download the lighting control program to system through serial from host PC. As a measurement result, a proposed lighting control system than the existing lighting control system were proved to be effective to the overall power consumption reduction.

The Development of Industrial Communication Monitoring Board using AVR (AVR을 이용한 산업용 통신 모니터링 보드 개발)

  • Eum, Sang-hee;Lee, Byong-Hoon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.6
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    • pp.1177-1182
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    • 2016
  • The most industrial instruments for monitoring and control are occurring the extension problem and the external protocol compatibility. In this paper, we developed the boards for the industrial communication monitoring that are able to convert the protocol in various communication between devices and instruments. These are consisted the main board and several sub-board. They can have extension using the main board connection. The sub-board support the each communication method or data transfer. The main board was used the Atmega 2560 Microprocessor of AVR series, and the sub-boards are have the Atmega 256 or Atmega 128 in the AVR series. We have designed to connect the sub-board using placed the 4 RS485 serial slots in the main board. The sub-boards were developed to support the analog and digital I/O. These are able to have monitoring by CAN and Ethernet communication. The experimental results, we obtained good data transfer rate and conversion rate.

THE SKELETAL STABILITY OF LE FORT I MAXILLARY ADVANCEMENT (Le Fort I 상악골전진술 후 안정성에 관한 연구)

  • Seo, Min-Gyo;Koo, Sung-Young;Kim, Eun-Ju;Leem, Dae-Ho;Shin, Hyo-Keun;Ko, Seung-O
    • Maxillofacial Plastic and Reconstructive Surgery
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    • v.32 no.2
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    • pp.149-153
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    • 2010
  • The purpose of this retrospective study was to evaluate relapse, comparing large and small maxillary advancements with four-plate rigid fixation and without bone grafting. All patients had skeletal class III malocclusion, and underwent bimaxillary surgery. Standardized cephalometric analysis by one examiner was performed on serial radiographs of 14 patients immediately before surgery, and within 1 week and at least 6 months postoperatively (mean 10 months). The group was divided into two subsets to determine whether the magnitude of relapse. In group 1 ($\leq$ 5 mm, n = 8), the average advancement was $4.0{\pm}0.9\;mm$, with a mean relapse of $0.1{\pm}0.5\;mm$. In group 2 (6-8 mm, n = 4), the average advancement was $6.8{\pm}0.9\;mm$, with a mean relapse of $0.7{\pm}0.4\;mm$. There was no statistical difference in the measured relapse among the groups. Maxillary advancement with a 1-piece Le Fort I osteotomy is a relatively stable procedure.

Register-Based Parallel Pipelined Scheme for Synchronous DRAM (동기식 기억소자를 위한 레지스터를 이용한 병렬 파이프라인 방식)

  • Song, Ho Jun
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.12
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    • pp.108-114
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    • 1995
  • Recently, along wtih the advance of high-performance system, synchronous DRAM's (SDRAM's) which provide consecutive data output synchronized with an external clock signal, have been reported. However, in the conventional SDRAM's which utilize a multi-stage serial pipelined scheme, the column path is divided into multi-stages depending on CAS latency N. Thus, as the operating speed and CAS latency increase, new stages must be added, thereby causing a large area penalty due to additinal latches and I/O lines. In the proposed register-based parallel pipelined scheme, (N-1) registers are located between the read data bus line pair and the data output buffer and the coming data are sequentially stored. Since the column data path is not divided and the read data is directly transmitted to the registers, the busrt read operation can easily be achieved at higher frequencies without a large area penalty and degradation of internal timing margin. Simulation results for 0.32um-Tech. 4-Bank 64M SDRAM show good operation at 200MHz and an area increment is less than 0.1% when CAS latency N is increased from 3 to 4.. This pipelined scheme is more advantageous as the operating frequency increases.

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Serial Changes in the Rate of Respiratory Metabolism of Olive Flounder, Paralichthys olivaceus Exposed to Intermittent Chlorination of Chlorine Dioxide ($CIO_2$) (이산화염소 (CIO2)의 간헐적 처리에 따른 넙치, Paralichthys olivaceus 호흡대사율의 경시적 변화)

  • Kim, Heung-Yun
    • Journal of fish pathology
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    • v.16 no.2
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    • pp.91-102
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    • 2003
  • The present study was investigated the effects of chlorine dioxide ($CIO_2$) on the rcspimtory metabolism of olive flounder (Parolichlhys olivaceus) imtermittently exposed to seawater chlorinated by $CIO_2$:. Oxygen consumption of flounder before and after once or twice $CIO_2$-treatment with 12 hr- or/and 24 hr-interval were serially measured with automatic intenniteent-flow respirometer system (AIRS). The oxygen consumption rates of flowKier exposed to 0.10 and 0.20 ppm$CIO_2$, were not different from the control fish prior to the once or twice chlorinations . On the other hand, the respiratory metabolic rates of flounder exposed to 0.30 ppm$CIO_2$ were significantly increased 15% and 22 - 23% after the once and twice chlorinations compared to the control fish. respectively. The flounder exposed In 0.40 and 0.50 ppm$CIO_2$: died within 4 hr and I hr. respectively. The elevation( respiratory metabolism in flounder exposed toO.30 ppm$CIO_2$ and above is considered due to physiological stress caused by $CIO_2$ exposure.

Analysis of Electrical Features of Serially and Parallelly connected Memristor Circuits (직렬 및 병렬연결 멤리스터 회로의 전기적 특성 해석)

  • Budhathoki, Ram Kaji;Sah, Maheshwar Pd.;Kim, Ju-Hong;Kim, Hyong-Suk
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.5
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    • pp.1-9
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    • 2012
  • Memristor which is known as fourth basic circuit element has been developed recently but its electrical characteristics are not still fully understood. Memristor has the incremental and decremental feature of the resistance depending upon the connected polarities. Also, its operational behavior become diverse depending on its connection topologies. In this work, electrical characteristics of diverse types of serial and parallel connections are investigated using the HP $TiO_2$ model. The characteristics are analyzed with pinched hystersis loops on the V-I plane when sine input signal is applied. The results of the work would be utilized usefully for analyzing the characteristics of memristor element and applications to logic circuit and neuron cells.

Design of a Bit-Serial Divider in GF(2$^{m}$ ) for Elliptic Curve Cryptosystem (타원곡선 암호시스템을 위한 GF(2$^{m}$ )상의 비트-시리얼 나눗셈기 설계)

  • 김창훈;홍춘표;김남식;권순학
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.12C
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    • pp.1288-1298
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    • 2002
  • To implement elliptic curve cryptosystem in GF(2$\^$m/) at high speed, a fast divider is required. Although bit-parallel architecture is well suited for high speed division operations, elliptic curve cryptosystem requires large m(at least 163) to support a sufficient security. In other words, since the bit-parallel architecture has an area complexity of 0(m$\^$m/), it is not suited for this application. In this paper, we propose a new serial-in serial-out systolic array for computing division operations in GF(2$\^$m/) using the standard basis representation. Based on a modified version of tile binary extended greatest common divisor algorithm, we obtain a new data dependence graph and design an efficient bit-serial systolic divider. The proposed divider has 0(m) time complexity and 0(m) area complexity. If input data come in continuously, the proposed divider can produce division results at a rate of one per m clock cycles, after an initial delay of 5m-2 cycles. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. Since the proposed divider can perform division operations at high speed with the reduced chip area, it is well suited for division circuit of elliptic curve cryptosystem. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomial, and has a unidirectional data flow and regularity, it provides a high flexibility and scalability with respect to the field size m.

Competition - Ecological Classification of the Prominent Paddy Weed Species around Bulrush(Scirpus juncoides) (올챙고랭이(Scirpus juncoides)를 중심으로 한 주요(主要) 논 잡초종(雜草種)의 벼 경합생태적(競合生態的) 분류(分類))

  • Guh, J.O.;Heo, S.M.
    • Korean Journal of Weed Science
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    • v.5 no.2
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    • pp.96-102
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    • 1985
  • A study on the competition-ecological classification of the 10 prominent paddy weed species around bulrush (Scirpus juneoides) to simplify the weed problem concept for the rice production. A serial assessments on the competition ability in space and dry matter production(nutrient depletion) of respective weed species and paddy rice, and the data were used to compute the phenotypic similarity by Single Link Clustering method. Both growth response of weed species in mono- and under the paddy rice standing was very similar (r = 0.969), but the reduction rate as affected by paddy rice standing was negatively correlated with the ability in space-competition(r=-0.513). Dendrogram of 10 weed species based on the phenotypic similarity computed in 4 characters in mono- and under the paddy rice standing was also similar, as Echinochloa c., Ludwigia p., Cyperus s., and Scirpus m. in I-group, Eleocharis k., Scirpus j, in II-group, and Juncus e., Potamogeton d. in III-group, respectively. Also, that of paddy rice to 10 weed species showed Fimbristylis m., Scirpus j., Eleocharis k., Scirpus m., Juncus e. in I-group, and Ludwigia p., Potamogeton d., Monochoria v. in II-group, respectively. The integrated dendrogram by the above two data indicate the I-group with Fimbristylis m., Scirpus j., Eleocharis k. and Juncus e., as higher growth response with relatively lower competition ability to paddy rice, II-group with Cyperus s., Echinochloa c., Potamogeton d., and Ludwigia p., as higher both in growth and competition, and the last, III-group with Monochoria v., and Scirpus m., as lower growth but higher competition, respectively.

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