• Title/Summary/Keyword: Sequence generator

Search Result 180, Processing Time 0.03 seconds

A Study on Analysis of Pseudo Noise Generator in Position Location Reporting System by W.F (Walsh 함수에 의한 PLR System에서의 의사잡음발생기 해석에 관한 연구)

  • An, Du-Su;Lee, Jae-Chun;Park, Jun-Hun
    • Proceedings of the KIEE Conference
    • /
    • 1987.07b
    • /
    • pp.1622-1624
    • /
    • 1987
  • In general, pseudo noise generator(PNG) used for PLR System consists of linear feedback shift register. Based on a W.F. representation of shift registers, a method for analyzing operational characters & sequence of PNG are studied. PNG is characterized by the time-recursive equation & PNG sequence is analyzed by the output state variable equation. Methods studied in this paper are illustrated by appropriate example.

  • PDF

SSR-Primer Generator: A Tool for Finding Simple Sequence Repeats and Designing SSR-Primers

  • Hong, Chang-Pyo;Choi, Su-Ryun;Lim, Yong-Pyo
    • Genomics & Informatics
    • /
    • v.9 no.4
    • /
    • pp.189-193
    • /
    • 2011
  • Simple sequence repeats (SSRs) are ubiquitous short tandem duplications found within eukaryotic genomes. Their length variability and abundance throughout the genome has led them to be widely used as molecular markers for crop-breeding programs, facilitating the use of marker-assisted selection as well as estimation of genetic population structure. Here, we report a software application, "SSR-Primer Generator " for SSR discovery, SSR-primer design, and homology-based search of in silico amplicons from a DNA sequence dataset. On submission of multiple FASTA-format DNA sequences, those analyses are batch processed in a Java runtime environment (JRE) platform, in a pipeline, and the resulting data are visualized in HTML tabular format. This application will be a useful tool for reducing the time and costs associated with the development and application of SSR markers.

VHDL Chip Set Design and implementation for Memory Tester Algorithm (Memory Tester 알고리즘의 VHDL Chip Set 설계 및 검증)

  • Jeong, Ji-Won;Gang, Chang-Heon;Choe, Chang;Park, Jong-Sik
    • Proceedings of the KIEE Conference
    • /
    • 2003.11c
    • /
    • pp.924-927
    • /
    • 2003
  • In this paper, we design the memory tester chip set playing an important role in the memory tester as central parts. Memory tester has the sixteen inner instructions to control the test sequence and the address and data signals to DUT. These instructions are saved in memory with each chip such as sequence chip and address/data generator chip. Sequence chip controls the test sequence according to instructions saved in the memory. And Generator chip generates the address and data signals according to instructions saved in the memory, too.

  • PDF

On Fast M-Gold Hadamard Sequence Transform (고속 M-Gold-Hadamard 시퀀스 트랜스폼)

  • Lee, Mi-Sung;Lee, Moon-Ho;Park, Ju-Yong
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.47 no.7
    • /
    • pp.93-101
    • /
    • 2010
  • In this paper we generate Gold-sequence by using M-sequence which is made by two primitive polynomial of GF(2). Generally M-sequence is generated by linear feedback shift register code generator. Here we show that this matrix of appropriate permutation has Hadamard matrix property. This matrix proves that Gold-sequence through two M-sequence and additive matrix of one column has one of major properties of Hadamard matrix, orthogonal. and this matrix show another property that multiplication with one matrix and transpose matrix of this matrix have the result of unit matrix. Also M-sequence which is made by linear feedback shift register gets Hadamard matrix property mentioned above by adding matrices of one column and one row. And high-speed conversion is possible through L-matrix and the S-matrix.

Image Encryption using Shrinking Generator based on CA (CA기반의 수축생성기를 이용한 영상 암호)

  • Choi, Un-Sook;Cho, Sung-Jin;Kim, Han-Doo;Kang, Sung-Won
    • The Journal of the Korea institute of electronic communication sciences
    • /
    • v.15 no.1
    • /
    • pp.179-184
    • /
    • 2020
  • Cellular automata (CA), which is known as a pseudo random number generator due to its excellent randomness, has various applications. Cho et al. designed a CA-based shrinking generator to generate a long period of nonlinear sequence. In addition, chaotic cat maps have been studied by many researchers as the complex nonlinear dynamics systems with sensitivity in initial conditions and unpredictable characteristics. In this paper, we propose a new image encryption method using nonlinear sequence generated by CA-based shrinking generator with maximum period and 3D chaotic cat map for high security.

A DVR Control for Compensating Unbalanced Voltage Dips of a DFIG System using Zero Sequence Components

  • Thinh, Quach Ngoc;Ko, Ji-Han;Kim, Dong-Wan;Kim, Eel-Hwan
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
    • /
    • v.27 no.2
    • /
    • pp.62-68
    • /
    • 2013
  • The dynamic voltage restorer (DVR) is an effective protection device for wind turbine generators based on doubly-fed induction generator (DFIG) that is operated under unbalanced voltage dip conditions. The compensating voltages of the DVR depend on the voltage dips and on the influence of the zero sequence component. The zero sequence component results in high insulation costs and asymmetry in terminal voltages. This paper proposes the use of a proportional-resonant controller in stationary reference frames for controlling zero sequence components in the DVR to protect the DFIG during unbalanced voltage dips. To enhance the proposed control method, a comparison is carried out between two cases: with and without using the control of a zero sequence component. Simulation results are presented to verify the effectiveness of the proposed control method by using the Psim simulation program.

Fast Self-Similar Network Traffic Generation Based on FGN and Daubechies Wavelets (FGN과 Daubechies Wavelets을 이용한 빠른 Self-Similar 네트워크 Traffic의 생성)

  • Jeong, Hae-Duck;Lee, Jong-Suk
    • The KIPS Transactions:PartC
    • /
    • v.11C no.5
    • /
    • pp.621-632
    • /
    • 2004
  • Recent measurement studies of real teletraffic data in modern telecommunication networks have shown that self-similar (or fractal) processes may provide better models of teletraffic in modern telecommunication networks than Poisson processes. If this is not taken into account, it can lead to inaccurate conclusions about performance of telecommunication networks. Thus, an important requirement for conducting simulation studies of telecommunication networks is the ability to generate long synthetic stochastic self-similar sequences. A new generator of pseu-do-random self-similar sequences, based on the fractional Gaussian nois and a wavelet transform, is proposed and analysed in this paper. Specifically, this generator uses Daubechies wavelets. The motivation behind this selection of wavelets is that Daubechies wavelets lead to more accurate results by better matching the self-similar structure of long range dependent processes, than other types of wavelets. The statistical accuracy and time required to produce sequences of a given (long) length are experimentally studied. This generator shows a high level of accuracy of the output data (in the sense of the Hurst parameter) and is fast. Its theoretical algorithmic complexity is 0(n).

An Improved Control Strategy Using a PI-Resonant Controller for an Unbalanced Stand-Alone Doubly-Fed Induction Generator

  • Phan, Van-Tung;Lee, Hong-Hee;Chun, Tae-Won
    • Journal of Power Electronics
    • /
    • v.10 no.2
    • /
    • pp.194-202
    • /
    • 2010
  • The main cause of degradation in an unbalanced stand-alone doubly-fed induction generator (DFIG) system is negative sequence components that exist in the generated stator voltages. To eliminate these components, a hybrid current controller composed of a proportional-integral controller and a resonant regulator is developed in this paper. The proposed controller is applied to the rotor-side converter of a DFIG system for the purpose of compensating the negative stator voltage sequences. The proposed current controller is implemented in a single positive rotating reference frame and therefore the controller can directly regulate both the positive and negative sequence components without the need for sequential decomposition of the measured rotor currents. In terms of compensation capability and accuracy, simulations and experimental results demonstrated the excellent performance of the proposed control method when compared to conventional vector control schemes.

Protection for a Wind Turbine Generator in a Large Wind Farm

  • Zheng, Tai-Ying;Kim, Yeon-Hee;Kang, Yong-Cheol
    • Journal of Electrical Engineering and Technology
    • /
    • v.6 no.4
    • /
    • pp.466-473
    • /
    • 2011
  • This paper proposes a protection algorithm for a wind turbine generator (WTG) in a large wind farm. To minimize the outage section, a protection relay for a WTG should operate instantaneously for an internal fault or a connected feeder fault, whereas the relay should not operate for an internal fault of another WTG connected to the same feeder or an adjacent feeder fault. In addition, the relay should operate with a delay for an inter-tie fault or a grid fault. An internal fault of another WTG connected to the same feeder or an adjacent feeder fault, where the relay should not operate, is determined based on the magnitude of the positive sequence current. To differentiate an internal fault or a connected feeder fault from an inter-tie fault or a grid fault, the phase angle of the negative sequence current is used to distinguish a fault type. The magnitude of the positive sequence current is then used to decide either instantaneous operation or delayed operation. The performance of the proposed algorithm is verified under various fault conditions with EMTP-RV generated data. The results indicate that the algorithm can successfully distinguish instantaneous operation, delayed operation, or non-operation depending on fault positions and types.

Application of Dynamic Probabilistic Safety Assessment Approach for Accident Sequence Precursor Analysis: Case Study for Steam Generator Tube Rupture

  • Lee, Hansul;Kim, Taewan;Heo, Gyunyoung
    • Nuclear Engineering and Technology
    • /
    • v.49 no.2
    • /
    • pp.306-312
    • /
    • 2017
  • The purpose of this research is to introduce the technical standard of accident sequence precursor (ASP) analysis, and to propose a case study using the dynamic-probabilistic safety assessment (D-PSA) approach. The D-PSA approach can aid in the determination of high-risk/low-frequency accident scenarios from all potential scenarios. It can also be used to investigate the dynamic interaction between the physical state and the actions of the operator in an accident situation for risk quantification. This approach lends significant potential for safety analysis. Furthermore, the D-PSA approach provides a more realistic risk assessment by minimizing assumptions used in the conventional PSA model so-called the static-PSA model, which are relatively static in comparison. We performed risk quantification of a steam generator tube rupture (SGTR) accident using the dynamic event tree (DET) methodology, which is the most widely used methodology in D-PSA. The risk quantification results of D-PSA and S-PSA are compared and evaluated. Suggestions and recommendations for using D-PSA are described in order to provide a technical perspective.