• Title/Summary/Keyword: Separated gate

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High Efficiency Power Amplifier Based on Digital Pre-Distortion (디지털전치왜곡 기반 고효율 전력증폭기 설계)

  • Kwon, Ki-Dae;Yoon, Wonsik
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.8
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    • pp.1847-1853
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    • 2014
  • The PAPR of the input signal is increased due to OFDMA signal in a mobile communication system. High efficiency of a power amplifier, which accounts for power consumption, is a very important key technology. Digital Pre-Distortion techniques were used to improve the linearity of the power amplifier. The Asymmetric Doherty scheme was used to improve the efficiency of the power amplifier. In this paper, we propose a new structure of Asymmetric Doherty. Drive power amplifier part is separated as main path and peak path, and phase shifter is employed to improve power combine characteristics of the Doherty Amplifier. Also, envelope tracking technology for drive gate bais in drive peak amplifier is used to improve efficiency.

Thermo-Sensitive Polyurethane Membrane with Controllable Water Vapor Permeation for Food Packaging

  • Zhou, Hu;Shit, Huanhuan;Fan, Haojun;Zhou, Jian;Yuan, Jixin
    • Macromolecular Research
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    • v.17 no.7
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    • pp.528-532
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    • 2009
  • The size and shape of free volume (FV) holes available in membrane materials control the rate of gas diffusion and its permeability. Based on this principle, a segmented, thermo-sensitive polyurethane (TSPU) membrane with functional gate, i.e., the ability to sense and respond to external thermo-stimuli, was synthesized. This smart membrane exhibited close-open characteristics to the size of the FV hole and water vapor permeation and thus can be used as smart food packaging materials. Differential scanning calorimetry (DSC), dynamic mechanical analysis (DMA), positron annihilation lifetimes (PAL) and water vapor permeability (WVP) were used to evaluate how the morphological structure of TSPU and the temperature influence the FV holes size. In DSC and DMA studies, TSPU with a crystalline transition reversible phase showed an obvious phase-separated structure and a phase transition temperature at $53^{\circ}C$ (defined as the switch temperature and used as a functional gate). Moreover, the switch temperature ($T_s$) and the thermal-sensitivity of TSPU remained available after two or three thermal cyclic processes. The PAL study indicated that the FV hole size of TSPU is closely related to the $T_s$. When the temperature varied cyclically from $T_s-10{\circ}C$ to $T_s+10^{\circ}C$, the average radius (R) of the FV holes of the TSPU membrane also shifted cyclically from 0.23 to 0.467 nm, exhibiting an "open-close" feature. As a result, the WVP of the TSPU membrane also shifted cyclically from 4.30 to $8.58\;kg/m^2{\cdot}d$, which produced an "increase-decrease" response to the thermo-stimuli. This phase transition accompanying significant changes in the FV hole size and WVP can be used to develop "smart materials" with functional gates and controllable water vapor permeation, which support the possible applications of TSPU for food packaging.

Experimental Study on Hydrodynamic Characteristics of Dam Break Flow for Estimation of Green Water Loading (청수현상 추정을 위한 댐 붕괴 흐름의 유체동역학적 특성에 관한 실험적 연구)

  • Hyung Joon Kim;Jong Mu Kim;Jae Hong Kim;Kwang Hyo Jung;Gang Nam Lee
    • Journal of the Society of Naval Architects of Korea
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    • v.60 no.2
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    • pp.120-134
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    • 2023
  • In this study, hydrodynamic characteristics of dam break flow were investigated by a series of experiments. The experiments were performed in a 2-D rectangular flume with obtaining instantaneous images of dam break flow to capture the free surface elevation, and pressure distributions on vertical wall and bottom of the flume. The initial water depth of the dam break flow was changed into 3 different heights, and the gate opening speed was changed during the experiments to study the effect of the gate speed in the dam break flow. Generation of dam break phenomena could be classified into three stages, i.e., very initial, relatively stable, and wall impact stages. The wall impact stage could be separated into 4 generation phases of wall impinge, run-up, overturning, and touchdown phases based on the deformation of the free surface. The free surface elevation were investigated with various initial water depth and compared with the analytic solutions by Ritter (1892). The pressures acting on the vertical wall and bottom were provided for the whole period of dam break flow varying the initial water depth and gate open speed. The measurement results of the dam break flow was compared with the hydrodynamic characteristics of green water phenomena, and it showed that the dam break flow could overestimate the green water loading based on the estimation suggested by Buchner (2002).

다결정 실리콘 Self-align에 의한 바이폴라 트랜지스터의 제작

  • Chae, Sang-Hun;Gu, Jin-Geun;Kim, Jae-Ryeon;Lee, Jin-Hyo
    • ETRI Journal
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    • v.7 no.4
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    • pp.11-14
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    • 1985
  • A polysilicon self-aligned bipolar n-p-n transistor structure is described, which can be used in high speed and high packing density LSI circuits The emitter of this transistor is separated less than $0.4\mum$ with base contact by polysilicon self-align technology. Through all the process, the active region of this device is not damaged. therefore a high performance device is obtained. Using the transistor with $3.0\mum$ design rules, a CML ring oscillator has per-gate minimum propagation delay time of 400 ps at 2.7 mW power consumption condition.

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The Study and characteristics of integrated CMOS sensor's packaging (집적화된 CMOS 센서의 팩키징 연구 및 특성 평가)

  • Roh, Ji-Hyoung;Kwon, Hyeok-Bin;Shin, Kyu-Sik;Cho, Nam-Kyu;Moon, Byung-Moo;Lee, Dae-Sung
    • Proceedings of the KIEE Conference
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    • 2009.07a
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    • pp.1551_1552
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    • 2009
  • In this paper, we presented the packaging technologies of CMOS ISFET(Ion Sensitive Field Effect Transistor) pH sensor using post-CMOS process and MCP(Multi Chip Packaging). We have proposed and developed two types of packaging technology. one is one chip, which sensing layer is deposited on the gate metal of standard CMOS ISFET, the other is two chip type, which sensing layer is separated from CMOS ISFET and connected by bonding wire. These proposed packaging technologies would make it easy to fabricate CMOS ISFET pH sensor and to make variety types of pH sensor.

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A New Dual-Gate SOI LIGBT by employing Separated Shorted Anode and Floating Ohmic Contact (분리된 단락애노드와 플로팅오믹접합을 사용한 새로운 SOI 이중게이트 수평형 절연게이트바이폴라트랜지스터)

  • Ha, Min-Woo;Lee, Seung-Chul;Oh, Jae-Keun;Jeon, Byung-Chul;Han, Min-Koo;Choi, Yearn-Ik
    • Proceedings of the KIEE Conference
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    • 2001.07c
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    • pp.1343-1345
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    • 2001
  • 본 논문은 스냅백을 효과적으로 제거하고 순방향 전압 강하를 줄이는 새로운 구조의 분리된 이중 게이트 SOI SA-LIGBT를 제안하였다. 제안된 소자는 분리된 단락 애노드와 플로팅 오믹 접합의 적용을 통해 스냅백이 성공적으로 제거되었고, 순방향전압강하는 전류밀도가 100A/$cm^2$일 때 기존의 SA-LIGBT에 비교해서 2V 감소된다. 또한 턴-오프 특성도 분리된 단락 애노드를 적용하였기 때문에 SA-LIGBT보다 개선되었다.

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DEVELOPMENT OF INTELLIGENT POWER UNIT FOR HYBRID FOUR-DOOR SEDAN

  • Aitaka, K.;Hosoda, M.;Nomura, T.
    • International Journal of Automotive Technology
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    • v.4 no.2
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    • pp.57-64
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    • 2003
  • The Intelligent Power Unit (IPU) utilized in Honda's Civic Hybrid Integrated Motor Assist (IMA) system was developed with the aim of making every component lighter, more compact and more efficient than those in the former model. To reduce energy loss, inverter efficiency was increased by fine patterning of the Insulated Gate Bipolar Transistor (IGBT) chips, 12V DC-DC converter efficiency was increased by utilizing soft-switching, and the internal resistance of the IMA battery was lowered by modifying the electrodes and the current collecting structure. These improvements reduced the amount of heat generated by the unit components and made it possible to combine the previously separated Power Control Unit (PCU) and battery cooling systems into a single system. Consolidation of these two cooling circuits into one has reduced the volume of the newly developed IPU by 42% compared to the former model.

A Study on Implementation of Out-of-Step Detection Algorithm using VHDL (VHDL을 이용한 동기탈조 검출 알고리즘 구현에 관한 연구)

  • Kim, Chul-Hwan;Kwon, O-Sang
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.55 no.5
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    • pp.179-184
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    • 2006
  • In a power system, an out-of-step condition causes a variety of risk such as serious damage to system elements, tripping of loads and generators, mal-operation of relays, etc. Therefore, it is very important to detect the out-of- step condition and take a proper measure. This paper presents a study on implementation of out-of-step detection algorithm using VHDL(Very high speed Hardware Description Language). The structure of out-of-step detection algorithm is analyzed for development of out-of-step detection relay on the FPGA(Field Programmable Gate Array). The out-of-step algorithm is separated to 4 parts: DFT IP, complex power calculation IP, out-of-step detection IP, control unit. Each parts are developed and simulated by using VHDL.

Character Level and Word Level English License Plate Recognition Using Deep-learning Neural Networks (딥러닝 신경망을 이용한 문자 및 단어 단위의 영문 차량 번호판 인식)

  • Kim, Jinho
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.16 no.4
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    • pp.19-28
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    • 2020
  • Vehicle license plate recognition system is not generalized in Malaysia due to the loose character layout rule and the varying number of characters as well as the mixed capital English characters and italic English words. Because the italic English word is hard to segmentation, a separate method is required to recognize in Malaysian license plate. In this paper, we propose a mixed character level and word level English license plate recognition algorithm using deep learning neural networks. The difference of Gaussian method is used to segment character and word by generating a black and white image with emphasized character strokes and separated touching characters. The proposed deep learning neural networks are implemented on the LPR system at the gate of a building in Kuala-Lumpur for the collection of database and the evaluation of algorithm performance. The evaluation results show that the proposed Malaysian English LPR can be used in commercial market with 98.01% accuracy.

The Fabrication of Polysilicon Self-Aligned Bipolar Transistor (다결정 실리콘 자기정렬에 의한 바이폴라 트랜지스터의 제작)

  • Chai, Sang Hoon;Koo, Yong Seo;Lee, Jin Hyo
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.6
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    • pp.741-746
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    • 1986
  • A novel n-p-n bipolar transistor of which emitter is self-aligned with base contact by polyilicon is developed for using in high speed and high packing density LSI circuits. The emitter of this transistor is separated less than 0.4 \ulcorner with base contact by self-aligh technology, and the emitter feature size is less than 3x5 \ulcorner\ulcorner Because the active region of this transistor is not damaged through all the process, it has excellent electric properties. Using the n-p-n transistors by 3.0\ulcorner design rules, a NTL ring oscillator has 380 ps, a CML ring oscillator has 390ps, and a I\ulcorner ring oscillator has 5.6ns of per-gate minimum propagation delay time.

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