• 마이크로전자및패키징학회지
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• 제11권2호
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• pp.29-35
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• 2004

65 nm급 게이트 유전체로의 $HfO_2$의 적용을 위해 hydrogen-terminate된 Si 기판과 ECR $N_2$ plasma를 이용하여 SiNx를 형성한 기판 위에 MOCVD를 이용하여 $HfO_2$를 증착하였다. $450^{\circ}C$에서 증착시킨 박막의 경우 낮은 carbon 불순물을 가지며 비정질 matrix에 국부적인 결정화와 가장 적은 계면층이 형성되었으며 이 계면층은 Hf-silicate임을 알 수 있었다. 또한 $900^{\circ}C$, 30초간 $N_2$분위기에서 RTA 결과 $HfO_2/Si$의 single layer capacitor의 경우 계면층의 증가로 인해 EOT가 열처리전(2.6nm)보다 약 1 nm 증가하였다. 그러나 $HfO_2/SiNx/Si$ stack capacitor의 경우 SiNx 계면층은 열처리후에도 일정하게 유지되었으며 $HfO_2$ 박막의 결정화로 열처리전(2.7nm)보다 0.3nm의 EOT 감소를 나타내었으며 열처리후에도 $4.8{\times}10^{-6}A/cm^2$의 매우 우수한 누설전류 특성을 가짐을 알 수 있었다.

• 전자공학회논문지CI
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• 제46권4호
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• pp.102-110
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• 2009

본 논문은 적외선영상(infrared image)에서 배경모델링 기반의 실시간 객체 탐지 기법과 고속 PPC(PowerPC) & FPGA(Field Programmable Gate Array) 기반 개방형 구조의 하드웨어 설계 방법을 제안한다. 개방형 구조는 하드웨어 및 소프트웨어의 이식이 용이하고, 확장, 호환성, 관리 및 유지보수 등이 편리한 장점이 있다. 제안된 배경모델링 방법을 개방형 구조에 탑재하기 위하여 입력영상에서 검색영역 템플릿을 성긴 블록으로 구성하여 탐색영역의 크기를 줄인다. 또한, 이전 프레임과 현재 프레임에서 영상의 흔들림이 발생했을 때 보정하기 위해 전역움직임 보상방법을 적용한다. 배경과 객체를 분리는 픽셀 밝기의 시간 분석을 통해 적응적 값을 적용한다. 분리된 객체주변에 발생하는 클러터 제거 방법은 중앙값 필터를 적용한다. 설계된 임베디드 시스템에서 배경모델링, 객체탐지, 중앙값 필터, 라벨링, 합병 등의 방법은 PPC에서 구현하였다. 실험결과 제안된 임베디드 시스템에서 전역 움직임 보정과 배경예측을 통해 실시간으로 객체가 탐지될 수 있음을 보였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.31-32
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• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]

• 한국자동차공학회논문집
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• 제25권1호
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• pp.92-102
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• 2017

For an automotive surveillance radar system, fast-chirp train based FMCW (Frequency Modulated Continuous Wave) radar is a very effective method, because clutter and moving targets are easily separated in a 2D range-velocity map. However, pedestrians with low echo signals may be masked by strong clutter in actual field. To address this problem, we proposed in the previous work a clutter cancellation and moving target indication algorithm using the coherent phase method. In the present paper, we initially composed the test set-up using a 24 GHz FMCW transceiver and a real-time data logging board in order to verify this algorithm. Next, we created two indoor test environments consisting of moving human and stationary targets. It was found that pedestrians and strong clutter could be effectively separated when the proposed method is used. We also designed and implemented these algorithms in FPGA (Field Programmable Gate Array) in order to analyze the hardware and time complexities. The results demonstrated that the complexity overhead was nearly zero compared to when the typical method was used.

• 대한건축학회논문집:계획계
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• 제35권7호
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• pp.63-72
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• 2019

The purpose of this study is to apply the types of urban street pattern and the shape of streets to the master plan of a religious community complexes. The street pattern is a framework of urban structure and to understand the urban structure is helpful to understand the nature of urban streets. By analysing the precedent researches, the types of street patterns are classified as a serial pattern, a branching pattern, a grid pattern and a web pattern. The street patterns are hierarchically composed and classified as a differential development and sequential development. There are boundaries and gates where the street space is differentiated to the more private level. The urban streets continue to the architectural streets such as arcades, deck streets, corridors, lobbies and halls. The purposes and results of the master plan of this religious community complexes are as follows. 1) The school area, housing area and service area are properly separated and connected. They are separated by the building masses and connected by the street space in between. 2) The street pattern of this complexes is a serial pattern where the streets are the center of each functional building groups. The entry square is divided by the symbolic building. The one branch is school street and the other is living street. These streets are combined again to the festival street. 3) The architectural streets are organically related to the urban streets. 4) Each street spaces are of adequate form according to its properties as a place. 5) There are boundaries or gates such as a gab between buildings, posts, arches and deck streets according to the relationship between streets.

• 대한전기학회논문지:전력기술부문A
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• 제48권12호
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• 센서학회지
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• 제9권3호
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• pp.182-189
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• 2000

미소 공간 내의 진공도를 측정하기 위하여 마이크로 진공 센서를 제작하였다. 동작 원리로서 전계 방출 전류가 진공도에 의존한다는 점을 이용하였고, 이를 위해 측면형 실리콘 전계 방출 소자를 제작하였다. 음극과 게이트, 그리고 양극을 분리하기 위하여 표면 미세가공을 이용하였으며, 제작된 소자는 $10^{-5}{\sim}10^{-8}\;Torr$ 범위의 진공도에서 $1.20{\sim}2.42\;{\mu}A$ 범위의 방출 전류 변화를 보였다.

• 한국농촌건축학회논문집
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• 제14권3호
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• pp.69-76
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• 2012

This study aims to investigate the mechanism that analysis of the layout-structure of the Traditional Village Oeam. It can identify through the division of area, the properties of layout residential type, the relationship between buildings and roads and location of buildings and a gate. Traditional Folk Village is our precious cultural heritage. However, now is time for our disappearing heritage due to the indiscriminate development. This study will good references for residential Complex in modern society. As a result of this study road in the center of village is divided into two areas. The road and stream plays an important role in the housing layout and composition of the village. Oeam village houses are separated by scale as large, middle, small scale housing. The courty yard is formed widely through a various of housing plan. So that ventilation and light is favorable even if the main house is high. Each house has the individuality with avoiding the village roads and using the byroads and stone wall. Therefore, each house can protect the privacy of houses.

• 건축역사연구
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• 제21권1호
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• pp.155-170
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• 2012

The purpose of this study is to understand the architectural space of Donggung(東宮), the Prince's Palace, and Dongjo(東朝), the King's Mother and Queen's living space, in the early Joseon Dynasty. The Royal palace can be divided into three parts, political space for king, living space for king and his family and government office. So first, we should to understand the characteristics of each space in the Royal Palace. Up to now we have looked at the architectural space of Donggung(東宮) and Dongjo(東朝) in Gyeongbokgung(景福宮), one of the Royal Palace, the result of this study is as followings. Donggung which was living space for Prince consisted of Jaseondang(資善堂), Seunwhadang(承華堂) and Kyejodang(繼照堂) in the era of King Sejong Kyejodang was demolished and Seunwhadang was destroyed by fire in King Jungjong era and was not rebuilded. This buildings The buildings consisted of Jeondang, Whudang, main gate, hapmun(閤門) and corridor or fence Donggung and Dongjo was separated wall Dong consisted of many buildings for Queen dowager, Queen and many royal concubines The arrangement of Donggung and Dongjo was assumed like as the Fig2.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.751-754
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• 2000

When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.