• 한국정보통신학회논문지
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• 제18권8호
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• pp.1847-1853
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• 2014

이동통신 시스템의 OFDMA 방식은 신호에 대한 PAPR(Peak to Average Power Ratio) 값의 증가를 가져왔다. 이동통신 시스템 전력 소모의 대부분을 차지하는 전력 증폭기에 대한 효율 개선은 매우 중요한 핵심 기술이다. 전력 증폭기의 선형 특성 개선을 위해 디지털전치왜곡 기술을 사용하였으며, 전력 증폭기의 효율 개선을 위해 비대칭 도허티(Asymmetric Doherty) 방식을 사용하였다. 본 논문에서는 기존 비대칭 도허티 구조와 다른 새로운 구조의 비대칭 도허티 구조를 제안하였다. 제안하는 새로운 구조의 비대칭 도허티 방식에서는 전력 증폭기 구동단을 주경로와 첨두경로로 분리하였으며, 위상 변환기를 이용하여 도허티 증폭기의 전력 결합 특성을 개선하였다. 또한 구동단 첨두 증폭기 gate bais에 대한 포락선 추적 기술을 적용하여 효율을 개선하였다.

• Macromolecular Research
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• 제17권7호
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• pp.528-532
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• 2009

The size and shape of free volume (FV) holes available in membrane materials control the rate of gas diffusion and its permeability. Based on this principle, a segmented, thermo-sensitive polyurethane (TSPU) membrane with functional gate, i.e., the ability to sense and respond to external thermo-stimuli, was synthesized. This smart membrane exhibited close-open characteristics to the size of the FV hole and water vapor permeation and thus can be used as smart food packaging materials. Differential scanning calorimetry (DSC), dynamic mechanical analysis (DMA), positron annihilation lifetimes (PAL) and water vapor permeability (WVP) were used to evaluate how the morphological structure of TSPU and the temperature influence the FV holes size. In DSC and DMA studies, TSPU with a crystalline transition reversible phase showed an obvious phase-separated structure and a phase transition temperature at $53^{\circ}C$ (defined as the switch temperature and used as a functional gate). Moreover, the switch temperature ($T_s$) and the thermal-sensitivity of TSPU remained available after two or three thermal cyclic processes. The PAL study indicated that the FV hole size of TSPU is closely related to the $T_s$. When the temperature varied cyclically from $T_s-10{\circ}C$ to $T_s+10^{\circ}C$, the average radius (R) of the FV holes of the TSPU membrane also shifted cyclically from 0.23 to 0.467 nm, exhibiting an "open-close" feature. As a result, the WVP of the TSPU membrane also shifted cyclically from 4.30 to $8.58\;kg/m^2{\cdot}d$, which produced an "increase-decrease" response to the thermo-stimuli. This phase transition accompanying significant changes in the FV hole size and WVP can be used to develop "smart materials" with functional gates and controllable water vapor permeation, which support the possible applications of TSPU for food packaging.

• 대한조선학회논문집
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• 제60권2호
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• pp.120-134
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• 2023

In this study, hydrodynamic characteristics of dam break flow were investigated by a series of experiments. The experiments were performed in a 2-D rectangular flume with obtaining instantaneous images of dam break flow to capture the free surface elevation, and pressure distributions on vertical wall and bottom of the flume. The initial water depth of the dam break flow was changed into 3 different heights, and the gate opening speed was changed during the experiments to study the effect of the gate speed in the dam break flow. Generation of dam break phenomena could be classified into three stages, i.e., very initial, relatively stable, and wall impact stages. The wall impact stage could be separated into 4 generation phases of wall impinge, run-up, overturning, and touchdown phases based on the deformation of the free surface. The free surface elevation were investigated with various initial water depth and compared with the analytic solutions by Ritter (1892). The pressures acting on the vertical wall and bottom were provided for the whole period of dam break flow varying the initial water depth and gate open speed. The measurement results of the dam break flow was compared with the hydrodynamic characteristics of green water phenomena, and it showed that the dam break flow could overestimate the green water loading based on the estimation suggested by Buchner (2002).

• ETRI Journal
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• 제7권4호
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• pp.11-14
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• 1985

바이폴라 소자로 구성된 회로가 양호한 특성을 갖기 위해서는 개별 소자의 동작 속도, 집적도 및 전력 소비 특성이 좋아야 한다. 그런데 지금까지 주로 사용해온 기존의 SBC 바이폴라 트랜지스터로는 이들 특성을 개선하는 데는 한계가 있었다. 일반적으로 바이폴라 트랜지스터는 면적이 줄어듦에 따라 이들 특성이 개선되므로 본 연구에서는 SBC 방법과는 다른 PSA 공정 방법을 개발하였다. 즉, 소자 격리에서의 종래의 PN 접합에 의한 방법과 다른 산화막에 의한 방법을 도입하였고 또한 에미터, 베이스 사이의 거리를 최소로 줄이기 위하여 다결정 실리콘에 의한 polysilicon self-align 방법으로 에미터 및 베이스를 형성시켰다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1551_1552
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• 2009

In this paper, we presented the packaging technologies of CMOS ISFET(Ion Sensitive Field Effect Transistor) pH sensor using post-CMOS process and MCP(Multi Chip Packaging). We have proposed and developed two types of packaging technology. one is one chip, which sensing layer is deposited on the gate metal of standard CMOS ISFET, the other is two chip type, which sensing layer is separated from CMOS ISFET and connected by bonding wire. These proposed packaging technologies would make it easy to fabricate CMOS ISFET pH sensor and to make variety types of pH sensor.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 C
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• pp.1343-1345
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• 2001

본 논문은 스냅백을 효과적으로 제거하고 순방향 전압 강하를 줄이는 새로운 구조의 분리된 이중 게이트 SOI SA-LIGBT를 제안하였다. 제안된 소자는 분리된 단락 애노드와 플로팅 오믹 접합의 적용을 통해 스냅백이 성공적으로 제거되었고, 순방향전압강하는 전류밀도가 100A/$cm^2$일 때 기존의 SA-LIGBT에 비교해서 2V 감소된다. 또한 턴-오프 특성도 분리된 단락 애노드를 적용하였기 때문에 SA-LIGBT보다 개선되었다.

• International Journal of Automotive Technology
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• 제4권2호
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• pp.57-64
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• 2003

The Intelligent Power Unit (IPU) utilized in Honda's Civic Hybrid Integrated Motor Assist (IMA) system was developed with the aim of making every component lighter, more compact and more efficient than those in the former model. To reduce energy loss, inverter efficiency was increased by fine patterning of the Insulated Gate Bipolar Transistor (IGBT) chips, 12V DC-DC converter efficiency was increased by utilizing soft-switching, and the internal resistance of the IMA battery was lowered by modifying the electrodes and the current collecting structure. These improvements reduced the amount of heat generated by the unit components and made it possible to combine the previously separated Power Control Unit (PCU) and battery cooling systems into a single system. Consolidation of these two cooling circuits into one has reduced the volume of the newly developed IPU by 42% compared to the former model.

• 대한전기학회논문지:전력기술부문A
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• 제55권5호
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• pp.179-184
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• 2006

In a power system, an out-of-step condition causes a variety of risk such as serious damage to system elements, tripping of loads and generators, mal-operation of relays, etc. Therefore, it is very important to detect the out-of- step condition and take a proper measure. This paper presents a study on implementation of out-of-step detection algorithm using VHDL(Very high speed Hardware Description Language). The structure of out-of-step detection algorithm is analyzed for development of out-of-step detection relay on the FPGA(Field Programmable Gate Array). The out-of-step algorithm is separated to 4 parts: DFT IP, complex power calculation IP, out-of-step detection IP, control unit. Each parts are developed and simulated by using VHDL.

• 디지털산업정보학회논문지
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• 제16권4호
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• pp.19-28
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• 2020

Vehicle license plate recognition system is not generalized in Malaysia due to the loose character layout rule and the varying number of characters as well as the mixed capital English characters and italic English words. Because the italic English word is hard to segmentation, a separate method is required to recognize in Malaysian license plate. In this paper, we propose a mixed character level and word level English license plate recognition algorithm using deep learning neural networks. The difference of Gaussian method is used to segment character and word by generating a black and white image with emphasized character strokes and separated touching characters. The proposed deep learning neural networks are implemented on the LPR system at the gate of a building in Kuala-Lumpur for the collection of database and the evaluation of algorithm performance. The evaluation results show that the proposed Malaysian English LPR can be used in commercial market with 98.01% accuracy.

• 대한전자공학회논문지
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• 제23권6호
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• pp.741-746
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• 1986

A novel n-p-n bipolar transistor of which emitter is self-aligned with base contact by polyilicon is developed for using in high speed and high packing density LSI circuits. The emitter of this transistor is separated less than 0.4 \ulcorner with base contact by self-aligh technology, and the emitter feature size is less than 3x5 \ulcorner\ulcorner Because the active region of this transistor is not damaged through all the process, it has excellent electric properties. Using the n-p-n transistors by 3.0\ulcorner design rules, a NTL ring oscillator has 380 ps, a CML ring oscillator has 390ps, and a I\ulcorner ring oscillator has 5.6ns of per-gate minimum propagation delay time.