• Journal of the Microelectronics and Packaging Society
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• v.11 no.2 s.31
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• pp.29-35
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• 2004

Hafnium-oxide gate dielectric films deposited by a metal organic chemical vapor deposition technique on a $N_2-plasma$ treated SiNx and a hydrogen-terminated Si substrate have been investigated. In the case of $HfO_2$ film deposited on a hydrogen-terminated Si substrate, suppressed crystallization with effective carbon impurity reduction was obtained at $450^{\circ}C$. X-ray photoelectron spectroscopy indicated that the interface layer was Hf-silicate rather than phase separated Hf-silicide and silicon oxide structure. Capacitance-voltage measurements show equivalent oxide thickness of about 2.6nm for a 5.0 nm $HfO_2/Si$ single layer capacitor and of about 2.7 nm for a 5.7 nm $HfO_2/SiNx/Si$ stack capacitor. TEM shows that the interface of the stack capacitor is stable up to $900^{\circ}C$ for 30 sec.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.4
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• pp.102-110
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• 2009

In this paper, we propose an object detection method for real-time in infrared (IR) images and PowerPC (PPC) and H/W design based on field programmable gate array (FPGA). An open H/W architecture has the advantages, such as easy transplantation of HW and S/W, support of compatibility and scalability for specification of current and previous versions, common module design using standardized design, and convenience of management and maintenance. Proposed background modeling for an open H/W architecture design decreases size of search area to construct a sparse block template of search area in IR images. We also apply to compensate for motion compensation when image moves in previous and current frames of IR sensor. Separation method of background and objects apply to adaptive values through time analysis of pixel intensity. Method of clutter reduction to appear near separated objects applies to median filter. Methods of background modeling, object detection, median filter, labeling, merge in the design embedded system execute in PFC processor. Based on experimental results, proposed method showed real-time object detection through global motion compensation and background modeling in the proposed embedded system.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.31-32
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• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]

• Transactions of the Korean Society of Automotive Engineers
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• v.25 no.1
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• pp.92-102
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• 2017

For an automotive surveillance radar system, fast-chirp train based FMCW (Frequency Modulated Continuous Wave) radar is a very effective method, because clutter and moving targets are easily separated in a 2D range-velocity map. However, pedestrians with low echo signals may be masked by strong clutter in actual field. To address this problem, we proposed in the previous work a clutter cancellation and moving target indication algorithm using the coherent phase method. In the present paper, we initially composed the test set-up using a 24 GHz FMCW transceiver and a real-time data logging board in order to verify this algorithm. Next, we created two indoor test environments consisting of moving human and stationary targets. It was found that pedestrians and strong clutter could be effectively separated when the proposed method is used. We also designed and implemented these algorithms in FPGA (Field Programmable Gate Array) in order to analyze the hardware and time complexities. The results demonstrated that the complexity overhead was nearly zero compared to when the typical method was used.

• Journal of the Architectural Institute of Korea Planning & Design
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• v.35 no.7
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• pp.63-72
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• 2019

The purpose of this study is to apply the types of urban street pattern and the shape of streets to the master plan of a religious community complexes. The street pattern is a framework of urban structure and to understand the urban structure is helpful to understand the nature of urban streets. By analysing the precedent researches, the types of street patterns are classified as a serial pattern, a branching pattern, a grid pattern and a web pattern. The street patterns are hierarchically composed and classified as a differential development and sequential development. There are boundaries and gates where the street space is differentiated to the more private level. The urban streets continue to the architectural streets such as arcades, deck streets, corridors, lobbies and halls. The purposes and results of the master plan of this religious community complexes are as follows. 1) The school area, housing area and service area are properly separated and connected. They are separated by the building masses and connected by the street space in between. 2) The street pattern of this complexes is a serial pattern where the streets are the center of each functional building groups. The entry square is divided by the symbolic building. The one branch is school street and the other is living street. These streets are combined again to the festival street. 3) The architectural streets are organically related to the urban streets. 4) Each street spaces are of adequate form according to its properties as a place. 5) There are boundaries or gates such as a gab between buildings, posts, arches and deck streets according to the relationship between streets.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• Journal of Sensor Science and Technology
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• v.9 no.3
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• pp.182-189
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• 2000

A micro-vacuum sensor was fabricated for the measurement of the vacuum level in micro-space. The fact that the field emission current was dependent on the environmental vacuum level was employed as an operating principle. The fabricated lateral-type field emitter triode with a cathode, a gate and a anode separated by using the surface micromachining process showed the emission current variation in the range of $1.20{\sim}2.42\;{\mu}A$ for the vacuum range of $10^{-5}{\sim}10^{-8}\;Torr$.

• Journal of the Korean Institute of Rural Architecture
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• v.14 no.3
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• pp.69-76
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• 2012

This study aims to investigate the mechanism that analysis of the layout-structure of the Traditional Village Oeam. It can identify through the division of area, the properties of layout residential type, the relationship between buildings and roads and location of buildings and a gate. Traditional Folk Village is our precious cultural heritage. However, now is time for our disappearing heritage due to the indiscriminate development. This study will good references for residential Complex in modern society. As a result of this study road in the center of village is divided into two areas. The road and stream plays an important role in the housing layout and composition of the village. Oeam village houses are separated by scale as large, middle, small scale housing. The courty yard is formed widely through a various of housing plan. So that ventilation and light is favorable even if the main house is high. Each house has the individuality with avoiding the village roads and using the byroads and stone wall. Therefore, each house can protect the privacy of houses.

• Journal of architectural history
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• v.21 no.1
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• pp.155-170
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• 2012

The purpose of this study is to understand the architectural space of Donggung(東宮), the Prince's Palace, and Dongjo(東朝), the King's Mother and Queen's living space, in the early Joseon Dynasty. The Royal palace can be divided into three parts, political space for king, living space for king and his family and government office. So first, we should to understand the characteristics of each space in the Royal Palace. Up to now we have looked at the architectural space of Donggung(東宮) and Dongjo(東朝) in Gyeongbokgung(景福宮), one of the Royal Palace, the result of this study is as followings. Donggung which was living space for Prince consisted of Jaseondang(資善堂), Seunwhadang(承華堂) and Kyejodang(繼照堂) in the era of King Sejong Kyejodang was demolished and Seunwhadang was destroyed by fire in King Jungjong era and was not rebuilded. This buildings The buildings consisted of Jeondang, Whudang, main gate, hapmun(閤門) and corridor or fence Donggung and Dongjo was separated wall Dong consisted of many buildings for Queen dowager, Queen and many royal concubines The arrangement of Donggung and Dongjo was assumed like as the Fig2.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.751-754
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• 2000

When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.