• 제목/요약/키워드: Semiconductor wafer fabrication

검색결과 153건 처리시간 0.025초

반도체 Wafer Fabrication 공정에서의 생산일정계획 (Production Scheduling in Semiconductor Wafer Fabrication Process)

  • 이군희;홍유신;김수영
    • 대한산업공학회지
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    • 제21권3호
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    • pp.357-369
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    • 1995
  • Wafer fabrication process is the most important and critical process in semiconductor manufacturing. The process is very complicated and hard to establish an efficient schedule due to its complexity. Furthermore, several performance indices such as due dates, throughput, cycle time and workstation utilizations are to be considered simultaneously for an efficient schedule, and some of these indices have negative correlations in performances each other. We develop an efficient heuristic scheduling algorithm; Hybrid Input Control Policy and Hybrid Dispatching Rule. Through numerical experiments, it is shown that the proposed Hybrid Scheduling Algorithm gives better performance compared with existing algorithms.

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Quantitative Exposure Assessment of Various Chemical Substances in a Wafer Fabrication Industry Facility

  • Park, Hyun-Hee;Jang, Jae-Kil;Shin, Jung-Ah
    • Safety and Health at Work
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    • 제2권1호
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    • pp.39-51
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    • 2011
  • Objectives: This study was designed to evaluate exposure levels of various chemicals used in wafer fabrication product lines in the semiconductor industry where work-related leukemia has occurred. Methods: The research focused on 9 representative wafer fabrication bays among a total of 25 bays in a semiconductor product line. We monitored the chemical substances categorized as human carcinogens with respect to leukemia as well as harmful chemicals used in the bays and substances with hematologic and reproductive toxicities to evaluate the overall health effect for semiconductor industry workers. With respect to monitoring, active and passive sampling techniques were introduced. Eight-hour long-term and 15-minute short-term sampling was conducted for the area as well as on personal samples. Results: The results of the measurements for each substance showed that benzene, toluene, xylene, n-butyl acetate, 2-methoxy-ethanol, 2-heptanone, ethylene glycol, sulfuric acid, and phosphoric acid were non-detectable (ND) in all samples. Arsine was either "ND" or it existed only in trace form in the bay air. The maximum exposure concentration of fluorides was approximately 0.17% of the Korea occupational exposure limits, with hydrofluoric acid at about 0.2%, hydrochloric acid 0.06%, nitric acid 0.05%, isopropyl alcohol 0.4%, and phosphine at about 2%. The maximum exposure concentration of propylene glycol monomethyl ether acetate (PGMEA) was 0.0870 ppm, representing only 0.1% or less than the American Industrial Hygiene Association recommended standard (100 ppm). Conclusion: Benzene, a known human carcinogen for leukemia, and arsine, a hematologic toxin, were not detected in wafer fabrication sites in this study. Among reproductive toxic substances, n-butyl acetate was not detected, but fluorides and PGMEA existed in small amounts in the air. This investigation was focused on the air-borne chemical concentrations only in regular working conditions. Unconditional exposures during spills and/or maintenance tasks and by-product chemicals were not included. Supplementary studies might be required.

접촉전도와 반투명 복사가 반도체 웨이퍼의 CVD 공정 중 열전달에 미치는 영향 (Effect of Contact Conductance and Semitransparent Radiation on Heat Transfer During CVD Process of Semiconductor Wafer)

  • 윤용석;홍혜정;송명호
    • 대한기계학회논문집B
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    • 제32권2호
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    • pp.149-157
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    • 2008
  • During CVD process of semiconductor wafer fabrication, maintaining the uniformity of temperature distribution at wafer top surface is one of the key factors affecting the quality of final products. Effect of contact conductance between wafer and hot plate on predicted temperature of wafer was investigated. The validity of opaque wafer assumption was also examined by comparing the predicted results with Discrete Ordinate solutions accounting for semitransparent radiative characteristics of silicon. As the contact conductance increases predicted wafer temperature increases and the differences between maximum and minimum temperatures within wafer and between wafer and hot plate top surface temperatures decrease. The opaque assumption always overpredicted the wafer temperature compared to semitransparent calculation. The influences of surrounding reactor inner wall temperature and hot plate configuration are then discussed.

데이터마이닝을 이용한 반도체 FAB공정의 수율개선 및 예측 (Application of Data mining for improving and predicting yield in wafer fabrication system)

  • 백동현;한창희
    • 지능정보연구
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    • 제9권1호
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    • pp.157-177
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    • 2003
  • 본 논문은 반도체 FAB공정의 수율개선 및 예측을 위해 데이터마이닝 기법을 적용한 사례를 소개한다. FAB 공정의 복잡성과 생산현장에서 수집되는 방대한 기술데이터로 인해 기존의 통계적 방법이나 엔지니어의 경험적 분석 방법만으로는 미처 파악하지 못하는 수율 저하 요인이 상당 수 존재한다. 본 논문은 먼저, FAB공정을 마친 웨이퍼에 불량 칩(chip)이 지리적으로 특정 위치에 집중적으로 발생하는 현상을 육안검사 대신 군집분석을 이용하여 데이터로부터 자동 판별할 수 있는 방법을 제안한다. 다음으로 연속패턴분석, 분류분석, RBF(Radial Base Function) 기법을 적용하여 수율 저하의 원인이 되는 문제 장비나 문제 파라미터를 신속, 정확하게 파악할 수 있도록 해 줄 뿐만 아니라 공정 진행 중인 제품의 미래 수율을 예측할 수 있도록 지원하는 방법을 제안한다. 또한 위 기법들을 반도체 FAB공정을 대상으로 국내 모 반도체 회사에서 정보시스템으로 구현한 Y2R-PLUS (Yield Rapid Ramp-up, Prediction, analysis & Up Support) 시스템을 소개한다.

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A Send-ahead Policy for a Semiconductor Wafer Fabrication Process

  • Moon, Ilkyeong
    • 한국경영과학회지
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    • 제18권1호
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    • pp.119-126
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    • 1993
  • We study a manufacturing process that is quite common in semiconductor wafer fabrication of semiconductor chip production. A machine is used to process a job consisting of J wafers. Each job requires a setup, and the i$_{th}$ setup for a job is sucessful with probability P$_{i}$. The setup is prone to failure, which results in the loss of expensive wafers. Therefore, a tiral run is first conducted on a small batch. If the set up is successful, the test is passed and the balance of the job can be processed. If the setup is unsuccessful, the exposed wafers are lost to scrap and the mask is realigned. The process then repeats on the balance of the job. We call this as send-ahead policy and consider general policies in which the number of wafers that are sent shead depend on the cost of the raw wafer, the sequence of success probabilities, and the balance of the job. We model this process and determine the expected number of good wafers per job,the expected time to process a job, and the long run average throughput. An algorithm to minimize the cost per good wafer subject to a demand constraint is provided.d.d.

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실리콘 웨이퍼 습식 식각장치 설계 및 공정개발 (Design of Single-wafer Wet Etching Bath for Silicon Wafer Etching)

  • 김재환;이용일;홍상진
    • 반도체디스플레이기술학회지
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    • 제19권2호
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    • pp.77-81
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    • 2020
  • Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.

시뮬레이션을 이용한 웨이퍼 FAB 공정에서의 병목 공정 탐지 프레임워크 (Bottleneck Detection Framework Using Simulation in a Wafer FAB)

  • 양가람;정용호;김대환;박상철
    • 한국CDE학회논문집
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    • 제19권3호
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    • pp.214-223
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    • 2014
  • This paper presents a bottleneck detection framework using simulation approach in a wafer FAB (Fabrication). In a semiconductor manufacturing industry, wafer FAB facility contains various equipment and dozens kinds of wafer products. The wafer FAB has many characteristics, such as re-entrant processing flow, batch tools. The performance of a complex manufacturing system (i.e. semiconductor wafer FAB) is mainly decided by a bottleneck. This paper defines the problem of a bottleneck process and propose a simulation based framework for bottleneck detection. The bottleneck is not the viewpoint of a machine, but the viewpoint of a step with the highest WIP in its upstream buffer and severe fluctuation. In this paper, focus on the classification of bottleneck steps and then verify the steps are not in a starvation state in last, regardless of dispatching rules. By the proposed framework of this paper, the performance of a wafer FAB is improved in on-time delivery and the mean of minimum of cycle time.

반도체 제조 공정에서 발생 가능한 부산물 (Exposure Possibility to By-products during the Processes of Semiconductor Manufacture)

  • 박승현;신정아;박해동
    • 한국산업보건학회지
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    • 제22권1호
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    • pp.52-59
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    • 2012
  • Objectives: The purpose of this study was to evaluate the exposure possibility of by-products during the semiconductor manufacturing processes. Methods: The authors investigated types of chemicals generated during semiconductor manufacturing processes by the qualitative experiment on generation of by-products at the laboratory and a literature survey. Results: By-products due to decomposition of photoresist by UV-light during the photo-lithography process, ionization of arsine during the ion implant process, and inter-reactions of chemicals used at diffusion and deposition processes can be generated in wafer fabrication line. Volatile organic compounds (VOCs) such as benzene and formaldehyde can be generated during the mold process due to decomposition of epoxy molding compound and mold cleaner in semiconductor chip assembly line. Conclusions: Various types of by-products can be generated during the semiconductor manufacturing processes. Therefore, by-products carcinogen such as benzene, formaldehyde, and arsenic as well as chemical substances used during the semiconductor manufacturing processes should be controlled carefully.

폴리이미드형 8인치 정전기척의 제조 (Fabrication of 8 inch Polyimide-type Electrostatic Chuck)

  • 조남인;박순규;설용태
    • 반도체디스플레이기술학회지
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    • 제1권1호
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    • pp.9-13
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    • 2002
  • A polyimide-type electrostatic chuck (ESC) was fabricated for the application of holding 8-inch silicon wafers in the oxide etching equipment. For the fabrication of the unipolar ESC, core technologies such as coating of polyimide films and anodizing treatment of aluminum surface were developed. The polyimide films were prepared on top of thin coated copper substrates for the good electrical contacts, and the helium gas cooling technique was used for the temperature uniformity of the silicon wafers. The ESC was essentially working with an unipolar operation, which was easier to fabricate and operate compared to a bipolar operation. The chucking force of the ESC has been measured to be about 580 gf when the applied voltage was 1.5 kV, which was considered to be enough force to hold wafers during the dry etching processing. The employment of the ESC in etcher system could make 8% enhancement of the wafer processing yield.

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오존을 이용한 반도체 웨이퍼 세정 및 PR 제거 공정 (Semiconductor Wafer Cleaning and PR Strip Processes using Ozone)

  • 채상훈;정현채;문세호;손영수
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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    • pp.1089-1092
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    • 2003
  • This paper has been studied on wafer cleaning and photoresist striping in semiconductor fabrication processes using ozone solved deionized water. In this work, we have developed high concentration ozone generating system and high contact ratio ozone solving system to get high efficiency DIO$_3$. Through this study, we obtained 11% ozone gas concentration, 99.5% of ozone efficiency and 51% of solubility in deionized water.

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