• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.85-85
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• 2007

최근 귀금속중의 하나인 Ruthenium(Ru)은 높은 일함수, 누설전류에 대한 높은 저항성등의 톡성으로 인해 캐패시터의 하부전극으로 각광받고 있다. 하부전극으로 증착된 Ru은 일반적으로 각 캐패시터의 분리와 평탄화를 위해 건식식각이 이루어진다. 하지만, 건식식각 공정중 유독한 $RUO_4$ 가스가 발생할 수 있으며, 불균일한 캐패시터 표면을 유발할 수 있다. 이러한 문제점들을 해결하기 위해 CMP 공정이 필요하게 되었다. 하지만, Ru은 화학적으로 매우 안정하기 때문에 Ru CMP 슬러리에 대한 연구가 필요하게 되었으며, 이에 대한 연구가 활발히 진행되고 있다. 본 연구에서는 Ru CMP 공정에서 Chemical A가 에칭제 및 산화제로 사용된 슬러리의 pH 변화와 pH 적정제에 따른 영향을 살펴보았다. Ru wafer를 이용하여 static etch rate, passivation film thickness와 wettability를 pH와 pH 적정제에 따라 비교해 보았다. 또한, pH 적정제로 $NH_4OH$와 TMAH를 이용하여 pH별 슬러리를 제작하고 CMP 공정을 실시하여 Ru의 removal rate을 측정하였다. $NH_4OH$와 TMAH의 경우 각각 130. 100 nm/min의 연마율이 측정된 pH 6에서 가장 높은 연마률을 보였으며, TMAH의 경우가 pH 전 구간에서 $NH_4OH$에 비해 낮은 연마율이 측정되었다. TEOS 에 대한 Ru의 선택비를 측정해 본 결과, $NH_4OH$의 경우 pH 8~9. TMAH의 경우 pH 6~7에서 높은 selectivity를 얻을 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.31-32
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• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]

• Journal of the Korean Society of Industry Convergence
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• v.23 no.6_2
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• pp.1051-1058
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• 2020

The chemical mechanical planarization (CMP) is a process of physically and chemically polishing the semiconductor substrate. The planarization quality of a substrate can be evaluated by the within wafer non-uniformity (WIWNU). In order to improve WIWNU, it is important to manage the pad profile. In this study, a device capable of non-contact measurement of the pad thickness profile was developed. From the measured pad profile, the profile of the pad surface and the groove was extracted using the envelope function, and the pad thickness profile was derived using the difference between each profile. Thickness profiles of various CMP pads were measured using the developed PMS and envelope function. In the case of IC series pads, regardless of the pad wear amount, the envelopes closely follow the pad surface and grooves, making it easy to calculate the pad thickness profile. In the case of the H80 series pad, the pad thickness profile was easy to derive because the pad with a small wear amount did not reveal deep pores on the pad surface. However, the pad with a large wear amount make errors in the lower envelope profile, because there are pores deeper than the grooves. By removing these deep pores through filtering, the pad flatness could be clearly confirmed. Through the developed PMS and the pad thickness profile calculation method using the envelope function, the pad life, the amount of wear and the pad flatness can be easily derived and used for various pad analysis.

• Tribology and Lubricants
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• v.40 no.2
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• pp.47-53
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• 2024

Surface topography plays a decisive role in determining the performance of several precision components. In particular, the surface roughness of semiconductor devices affects the precision of the circuit. In this regard, the surface topography of a given surface needs to be appropriately assessed. Typically, the average roughness is used as one of the main indicators of surface finish quality because it is influenced by both dynamic and static parameters. Owing to the increasing demand for such accurate and reliable surface measurement systems, studies are continuously being conducted to understand the parameters of surface roughness and measure the average roughness with high reliability. However, the differences in the measurement methods of surface roughness are not clearly understood. Hence, in this study, the surface roughness of the back of a silicon wafer was measured using both contact and noncontact methods. Subsequently, a comparative analysis was conducted according to various surface roughness parameters to identify the differences in surface roughness depending on the measurement method. When using a 3D laser confocal microscope, even smaller surface asperities can be measured compared with the use of a 3D profiler. The results are expected to improve the understanding of the surface roughness characteristics of precision components and be used as a useful guideline for selecting the measurement method for surface topography assessment.

• Journal of the Korea Organic Resources Recycling Association
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• v.31 no.1
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• pp.35-45
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• 2023

In this study, the sludge formation in the wastewater drain from the advanced packaging process mechanisms are revealed as well as the key factors, materials, and sludge prevention methods using surfactant. Compared with that of conventional packaging process, advanced packaging process employ similar process to the semiconductor fabrication process, and thus many processes may generate wastewater. In specific, a large amount of wastewater may generate during the carrier wafer bonding, photo, development, and carrier wafer debonding processes. In order to identify the key factors for the formation of sludge during the advanced packaging process, six types of chemicals including bonding glue, HMDS, photoresist (PR), PR developer, debonding cleaner, and water are utilized and mixing evaluation is assessed. As a result, it is confirmed that the black solid sludge is formed, which is originated by the sludge seed formation by hydrolysis/dehydration reaction of HMDS and sludge growth via hydrophobic-hydrophobic binding with sludge seed and PR. For the sludge prevention investigation, three surfactants of CTAB, PEG, and shampoo are mixed with the key materials of sludge, and it is confirmed that the sludge formations are successfully suppressed. The underlying mechanism behind the sludge formation is that the carbon tails of the surfactant bind to PR with hydrophobic-hydrophobic interaction and inhibit the reaction with HMDS-based slurry seeds to prevent the sludge formation. In this regard, it is expected that various problems like clogging in drains and pipes during the advanced packaging process may effectively solve by the injection of surfactants into the drains.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.406-406
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• 2016

To get high efficiency n-type crystalline silicon solar cells, passivation is one of the key factor. Tunnel oxide (SiO2) reduce surface recombination as a passivation layer and it does not constrict the majority carrier flow. In this work, the passivation quality enhanced by different chemical solution such as HNO3, H2SO4:H2O2 and DI-water to make thin tunnel oxide layer on n-type crystalline silicon wafer and changes of characteristics by subsequent annealing process and firing process after phosphorus doped amorphous silicon (a-Si:H) deposition. The tunneling of carrier through oxide layer is checked through I-V measurement when the voltage is from -1 V to 1 V and interface state density also be calculated about $1{\times}1012cm-2eV-1$ using MIS (Metal-Insulator-Semiconductor) structure . Tunnel oxide produced by 68 wt% HNO3 for 5 min on $100^{\circ}C$, H2SO4:H2O2 for 5 min on $100^{\circ}C$ and DI-water for 60 min on $95^{\circ}C$. The oxide layer is measured thickness about 1.4~2.2 nm by spectral ellipsometry (SE) and properties as passivation layer by QSSPC (Quasi-Steady-state Photo Conductance). Tunnel oxide layer is capped with phosphorus doped amorphous silicon on both sides and additional annealing process improve lifetime from $3.25{\mu}s$ to $397{\mu}s$ and implied Voc from 544 mV to 690 mV after P-doped a-Si deposition, respectively. It will be expected that amorphous silicon is changed to poly silicon phase. Furthermore, lifetime and implied Voc were recovered by forming gas annealing (FGA) after firing process from $192{\mu}s$ to $786{\mu}s$. It is shown that the tunnel oxide layer is thermally stable.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.1
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• pp.603-608
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• 2018

Although the voltage-applied discharge method is most widely used in the semiconductor and display industries, periodic management costs are incurred because the method causes defects due to the absorption of ambient fine dust and causes emitter tip contamination due to the discharge. The emitter tip contamination problem is caused by the accumulation of fine particles in ambient air due to the corona discharge of the ionizer. Fuzzy ball generation accelerates the wear of the emitter tip and deteriorates the performance of the ionizer. Although a mechanical cleaning method using a manual brush or an automatic brush is effective for contaminant removal, it requires management of additional mechanical parts by the user. In some cases, contaminants accumulated in the emitter may be transferred to the wafer or product. In order to solve this problem, we developed an ionizer for a clean environment that can remove the pencil-type emitter tip and directly ionize the surrounding gas molecules using the tungsten wire located inside the ion tank. As a result of testing and certification by the Korea Institute of Machinery and Materials, the average concentration was $0.7572particles/ft^3$, the decay time was less than two seconds, and the ion valance was 7.6 V, which is satisfactory.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.3 s.40
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• pp.47-51
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• 2006

Recently, CMP (Chemical Mechanical Polishing) is one of very important processing in semiconductor technology because of large integration and application of design role. CMP is a planarization process of wafer surface using the chemical and mechanical reactions. One of the most important components of the CMP system is the polishing pad. During the CMP process, the pad itself becomes smoother and glazing. Therefore it is necessary to have a pad conditioning process to refresh the pad surface, to remove slurry debris and to supply the fresh slurry on the surface. A conditioning disk is used during the pad conditioning. There are diamonds on the surface of diamond disk to remove slurry debris and to polish pad surface slightly, so density, shape and size of diamond are very important factors. In this study, we characterized diamond disk with 9 kinds of sample.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.16 no.3
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• pp.116-120
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• 2006

We have investigated plasma spray coated $Al_2O_3$ layers on Al-60 series substrates for development of wafer electrostatic chuck in semiconductor dry etching system. Samples were prepared without/with cooling bar on backside of samples, at various distances, and with different powder feed rates. There were many cracks and pores in the $Al_2O_3$ layers coated on Al-60 series substrates without cooling bar on the backside of samples. But the cracks and pores were almost disappeared in the $Al_2O_3$ layers on Al-60 series substrates coated with cooling bar on the back side of samples, 15 g/min. powder feed rate and various 60, 70, 80 mm working distances. Then the surface morphology was not changed with various working distances of 60, 70, 80 mm. When the powder feed rate was changed from 15 g/min to 20 g/min, the crack did not appear, but few pores appeared. Also the $Al_2O_3$ layer was coated with many small splats compared with $Al_2O_3$ layer coated with 15 g/min powder feed rate. The deposited rate of $Al_2O_3$ layer was higher when the process was done without cooling bar on the back side of sample than that with cooling bar on the back side of sample.

• Journal of Sensor Science and Technology
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• v.1 no.2
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• pp.173-181
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• 1992

Tantalum pentoxide($Ta_{2}O_{5}$) thin films on p-type (100) silicon wafer were fabricated by RF reactive sputtering. Physical properties and structure of the specimens were examined by XRD and AES. From the C-V analysis, the dielectric constant of $Ta_{2}O_{5}$ films was in the range of 10-12 in the reactive gas atmosphere in which 10% of oxygen gas is mixed. The ratio of Ta : 0 was 1 : 2 and 1 : 2.49 by AES and RBS examination, respectively. The heat-treatment at $700^{\circ}C$ in $O_{2}$ ambient led to induce crystallization. When the heat-treatment temperature was $1000^{\circ}C$, the dielectric constant was 20.5 in $O_{2}$ ambient and 23 in $N_{2}$ ambient, respectively. The crystal structure of $Ta_{2}O_{5}$ film was pseudo hexagonal of ${\delta}-Ta_{2}O_{5}$. The flat band voltage shift(${\Delta}V_{FB}$) of the specimens and the leakage current density were decreased for higher oxygen mixing ratio. The maximum breakdown field was 2.4MV/cm at the oxygen mixing ratio of 10%. The $Ta_{2}O_{5}$ films will be applicable to hydrogen ion sensitive film and gate oxide material for memory device.