• 제목/요약/키워드: Semiconductor test equipment

검색결과 98건 처리시간 0.03초

웨이퍼 정렬기의 SECS/GEM통신 구현 및 운용시험 (Implementation of SECS/GEM Communication Protocol for Wafer Aligner)

  • 조재근;박홍래;유준
    • 대한전자공학회:학술대회논문집
    • /
    • 대한전자공학회 2003년도 하계종합학술대회 논문집 V
    • /
    • pp.2553-2556
    • /
    • 2003
  • In the semiconductor equipment industry, the SECS/GEM protocol has been recognized as the communication standard, but in our 300mm wafer aligner being developed, this capability has not been equipped yet. In this study, we present the realization of SECS-I, SECS-II and HSMS communication protocol between factory host computer and wafer aligner. Its validity is shown in actual test environment.

  • PDF

장비/부품의 신뢰성 평가 시스템 구축 방안 (Reliability Test System for Semiconductor Equipment & Part)

  • 황희융;설용태;이희환;차옥환
    • 한국산학기술학회:학술대회논문집
    • /
    • 한국산학기술학회 2002년도 춘계학술발표논문집
    • /
    • pp.93-95
    • /
    • 2002
  • 반도체 제조장비는 매우 높은 정밀도와 신뢰성이 요구되는 초정밀 시스템으로서 개발이 완료되어 실제 생산라인에 투입되기까지는 오랜 시간 동안 엄격한 시험평가를 통하여 신뢰성이 입증되어야 한다. 그러나 국내 중소 업계의 경우 고가 시험평가 설비를 보유하고 있지 않아 연구개발에 많은 어려움을 겪고 있다. 본 과제는 반도체 제조장비와 부품의 신뢰성 평가를 위한 시스템 구축방안에 대한 사항이다.

처짐저감을 위한 OLED 증착 마스크-프레임 구조체

  • 문병민;정남희;조창상;김국원
    • 한국반도체및디스플레이장비학회:학술대회논문집
    • /
    • 한국반도체및디스플레이장비학회 2007년도 춘계학술대회
    • /
    • pp.164-168
    • /
    • 2007
  • Deformation of a shadow mask is one of the problems encountered during the deposition of organic materials for manufacturing large size OLED. The larger the glass substrate, the larger the shadow mask becomes. But as the size of the shadow mask increases, its deformation becomes more severe, thereby making it difficult to deposit organic materials in a precise pattern on a substrate. In this paper, a new type mask-frame structure is proposed. The proposed mask-frame structure making a curved mask has the ability of reducing drooping of mask. The test frame is fabricated and evaluation experiments are performed.

  • PDF

진공 환경내 실시간 입자 모니터링 시스템의 개발 및 성능평가 (Development and Performance Test of In-situ Particle Monitoring System using Ion-counter in Vacuum Environments)

  • 안강호;김용민;권용택
    • 반도체디스플레이기술학회지
    • /
    • 제5권1호
    • /
    • pp.45-49
    • /
    • 2006
  • In this paper, a new method that monitors the quantity of particles using ion-counter in vacuum environment is introduced. In-situ particle monitoring (ISPM) system is composed by Gerdien type ion-counter (house-made), DC power supply and electrometer. The ion-counter applied by positive voltage detects only positive charged particles. Therefore the particles to be detected should be in known charge state for further data analysis. ion-counter is installed at the exhaust line of process equipment where the pressure loss is structurally low. ISPM system performance has been verified with SMPS (Scanning Mobility Particle Sizer) system. The correlation coefficient is above 0.98 at the particle size range of $20{\sim}300nm$ in diameter with identified charge distribution under $0.1{\sim}10.0$ Torr.

  • PDF

Load-Adaptive Address Energy Recovery Technique for Plasma Display Panel

  • 이준영
    • 한국반도체및디스플레이장비학회:학술대회논문집
    • /
    • 한국반도체및디스플레이장비학회 2005년도 춘계 학술대회
    • /
    • pp.192-200
    • /
    • 2005
  • A high speed address recovery technique for AC plasma display panel(PDP) is proposed. By removing the GND switching operation, the recovery speed can be increased and switching loss due to GND switch also becomes to be reduced. The proposed method is able to perform load-adaptive operation by controlling the voltage level of energy recovery capacitor, which prevents increasing inefficient power consumption caused by circuit loss during recovery operation. Thus, th e technique shows the minimum address power consumption according to various displayed images, different from prior methods operating in fixed mode regardless of images. Test results with 50' HD single- scan PDP(resolution : $1366{\times}768$) show that less than 350ns of recovery time is successfully accomplished and about $54\%$ of the maximum power consumption can be reduced, tracing minimum power consumption curves.

  • PDF

나노 세리아 슬러리에 첨가된 연마입자와 첨가제의 농도가 CMP 연마판 온도에 미치는 영향

  • 김성준;강현구;김민석;박재근
    • 한국반도체및디스플레이장비학회:학술대회논문집
    • /
    • 한국반도체및디스플레이장비학회 2003년도 추계학술대회 발표 논문집
    • /
    • pp.122-125
    • /
    • 2003
  • We investigated the effect of the abrasive and additive concentrations in Nano ceria slurry on the pad surface temperature under varying pressure through chemical mechanical polishing (CMP) test using blanket wafers. The pad surface temperature after CMP increased with the abrasive concentration and decreased with increase of the additive concentration in slurries for the constant down pressure. A possible mechanism is that the additive adsorbed on the film surface during polishing decreases the friction coefficient, hence the pad surface temperature gets lower with increase of the additive concentration. This difference of temperature was more remarkable for the higher concentration of abrasives. In addition, in-situ measurement of spindle motor was carried out during oxide and nitride polishing. The averaged motor current for oxide film was higher than that for nitride film, which means the higher friction coefficient.

  • PDF

감쇄위상변위마스크를 사용하는 메탈레이어 리토그라피공정의 오버레이 보정

  • 이우희;이준하;이흥주
    • 한국반도체및디스플레이장비학회:학술대회논문집
    • /
    • 한국반도체및디스플레이장비학회 2004년도 춘계학술대회 발표 논문집
    • /
    • pp.159-162
    • /
    • 2004
  • Problems of overlap errors and sidelobe printing by the design rule reduction in the lithography process using attenuated phase-shifting masks(attPSM) have been serious. Overlap errors and sidelobes can be simultaneously solved by the rule-based correction using scattering bars with the rules extracted from test patterns. Process parameters affecting the attPSM lithography simulation have been determined by the fitting method to the process data. Overlap errors have been solved applying the correction rules to the metal patterns overlapped with contact/via. Moreover, the optimal insertion rule of the scattering bars has made it possible to suppress the sidelobes and to get additional pattern fidelity at the same time.

  • PDF

COF(Chip On Film)에서의 Polyimide/Buffer layer/Cu 접착력 향상

  • 이재원;김상호;이지원;홍순성
    • 한국반도체및디스플레이장비학회:학술대회논문집
    • /
    • 한국반도체및디스플레이장비학회 2004년도 춘계학술대회 발표 논문집
    • /
    • pp.101-107
    • /
    • 2004
  • 각종 전자기기의 소형화, 고성능화 요구에 따라 회로 또는 기판의 고집적화에 따른 대안으로 도입된 COF(Chip On Film)공정에서 PI(polyimide)/buffer layer/Cu의 접착력 개선을 목적으로 본 연구가 진행 되었다. 그리고 buffer layer로써 Cr을 증착 할 때 부착력의 개선을 목적으로 개질처리를 할 때는 RF plasma장비를 사용하였다. 실험 변수로는 peel strength에 대한 buffer layer의 종류와 증착시간, 표면 개질처리시 $O_2$/Ar비이다. Buffer layer의 종류에 따른 접착력은 Cr보다 Ni이 우수하였고 peel strength와 Cu THK는 같은 buffer layer의 증착 structure에서 비례 관계를 나타냈으며, Cr의 증착 시간과 Cu의 증착 시간을 변수로 peel strength test한 값은 Cr증착시간이 30초, Cu증착시간이 20분일때 40g/mm로 최적의 접착력이 나타났다. 증착전 PI의 개질 처리시 $O_2$/Ar 유량비에 따른 peel strength값은 $O_2$/Ar유량비가 증가 할수록 향상되었으며, 2/5에서 최고값인 58g/mm가 나타났다. 그 이상에서는 오히려 감소하였다.

  • PDF

초정밀 선형 모터의 열.진동 분석

  • 임경화;이우영;설진수;김현철
    • 한국반도체및디스플레이장비학회:학술대회논문집
    • /
    • 한국반도체및디스플레이장비학회 2004년도 춘계학술대회 발표 논문집
    • /
    • pp.163-168
    • /
    • 2004
  • Linear motor can directly apply to the system needed linear mot ions without rotary mot ions. To control a high-speed and high-resolution, the development of the linear motors is recently required in the high-integrated and speed process industry. This paper presents vibration analyses as well as measurement standards of the newly developed linear motors through analyzing the vibration characteristics and thermal behaviors of the advanced products. Vibration experiments are conducted for identifying the hysteresis and vibration level during operation. They are also included in the modal test to analyze the vibration. Analytic data using Finite Element Method (FEM) are compared with the results of the modal. Loss of temperature generated the linear motor leads to a serious deformation within its parts. The thermal behaviors are very important factor in linear motor. The FEM and experiments make it possible to understand these characteristics.

  • PDF

Development of Process and Equipment for Roll-to-Roll convergence printing technology

  • 김동수;배성우;김충환
    • 한국재료학회:학술대회논문집
    • /
    • 한국재료학회 2010년도 춘계학술발표대회
    • /
    • pp.19.1-19.1
    • /
    • 2010
  • The process of manufacturing printed electronics using printing technology is attracting attention because its process cost is lower than that of the conventional semiconductor process. This technology, which offers both a lower cost and higher productivity, can be applied in the production of organic TFT (thin film transistor), solar cell, RFID(radio frequency identification) tag, printed battery, E-paper, touch screen panel, black matrix for LCD(liquid crystal display), flexible display, and so forth. In general, in order to implement printed electronics, narrow width and gap printing, registration of multi-layer printing by several printing units, and printing accuracy of under $20\;{\mu}m$ are all required. These electronic products require high precision to the degree of tens of microns - in a large area with flexible material, and mass productivity at low cost. As such, the roll-to-roll printing process is attracting attention as a mass production system for these printed electronic devices. For the commercialization of this process, two basic electronic ink technologies, such as conductive ink and polymers, and printing equipment have to be developed. Therefore, this paper addressed basis design and test to develop fine patterning equipment employing the roll-to-roll printing equipment and electronic ink.

  • PDF