• 제목/요약/키워드: Semiconductor test equipment

검색결과 98건 처리시간 0.029초

반도체 테스트 핸들러 픽커 검사장비 프레임에 대한 진동해석 (Vibration Analysis on the Inspection Equipment Frame of a Semiconductor Test Handler Picker)

  • 김영춘;김영진;국정한;조재웅
    • 한국산학기술학회논문지
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    • 제15권8호
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    • pp.4815-4820
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    • 2014
  • 최근에 반도체 칩이 소형화, 대용량화, 고집적화가 되고 있어 그 정밀도 및 신뢰성의 확보를 위해 반도체 테스트 핸들러 장비에서 픽앤플레이스의 개발이 필요하다. 본 연구에서는 반도체 테스트 핸들러 픽커 검사장비 프레임에 대한 진동해석을 하여 고유진동수와 하모닉 반응의 특성을 연구하였다. 해석모델로서는 세 가지 모델로서 픽앤플레이스 장치가 위 가이드라인의 왼쪽에 있는 경우(Case 1), 가운데에 있는 경우(Case 2) 및 오른쪽에 있는 경우(Case 3)이다. 이 프레임 모델들에 대해서 6차 모드까지의 고유진동수 범위는 80Hz~500Hz가 된다. Harmonic Response 해석 결과, 프레임에 공진이 발생할 때, Case 2는 Case 1과 Case 3보다 더 큰 52.802MPa의 최대 등가응력을 나타났다. 세 모델 중, Case 2의 경우가 진동에 의한 파손에 가장 강함을 알 수 있다. 본 연구의 해석 결과를 이용하여 시스템의 안전한 작업환경으로 실제 적용할 수 있는 모델 설계가 효율적으로 가능하다고 사료된다.

주파수 응답함수를 이용한 고정밀장비의 진동 허용규제치 결정기법에 관한 연구 (A Study on the Determination Vibration criteria for High Technology Facilities using FRF - Impact Test-)

  • 이홍기;박해동;김두훈;김사수
    • 한국소음진동공학회:학술대회논문집
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    • 한국소음진동공학회 1996년도 추계학술대회논문집; 한국과학기술회관, 8 Nov. 1996
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    • pp.377-385
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    • 1996
  • In the case of a precision equipment, it requires a vibration free environment to provide its proper function. Especially, lithography and inspection devices, which have sub-nanometer class high accuracy and resolution, have come to necessity for producing more improved giga class semiconductor wafers. This high technology equipments require very strict environmental vibration standard in proportion to the accuracy of the manufacturing, inspecting devices. The vibration criteria are usually obtained either by the real vibration exciting test on the equipment or by the analytical calculation. the former is accurate but requires a great deal of time and efforts while the latter lacks reliability. this paper proposes a new method to solve this problem at a time. the permissible vibration level to a precision equipment can be easily obtained by analyzing a process of Frequency Response Function. This paper also demonstrates its effectiveness by applying the proposed method to finding the vibration criteria of a Computer Hard Disk Drive by impact Test.

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반도체장비용 오링의 종합 신뢰성 평가기술에 관한 연구 (A Study on the Reliability Evaluation System for O-ring of Semiconductor Equipments)

  • 김동수;김광영;최병오;박화영
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2001년도 춘계학술대회 논문집
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    • pp.613-617
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    • 2001
  • The test items like as endurance, air leakage and oil endurance test is requested for reliability evaluation about O-ring which is a kind of core machinery accessories of semi-conduct manufacturing equipment. For verification of these, we design and manufactured a test system for endurance, air leakage and oil endurance of O-ring for semi-conduct manufacturing equipment, and also performed the test for two kinds of O-ring, as it were Viton and Kalretz. The characteristics of this test equipment consist in realization of the test conditions of semi-conduct manufacturing equipment and satisfying the test method. The test conditions are cut gas, vacuum grade, temperature and revolution numbers in the endurance test system, vacuum grade and temperature in the air leakage test system, temperature and time in the oil endurance test system. The separating test results for wearing which is an oil endurance test item, the wearing index of domestic produced Viton O-ring is higher than foreign product by 2%, wearing rate of Kalretz O-ring better than Viton O-ring by 17%, and particles existed in various place. The test result of air leakage which is measured through the RGA sensor used Helium, the vacuum grade was $10^-3$Torr. And the test result of oil endurance, the volume change rate was 7~15%. Hereafter, we intend to analysis the reliability test evaluation and to utilize for domestic manufacturing companies by establishing data base and developing reliability softwares.

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충격시험을 이용한 고정밀장비의 진동허용규제치 결정기법에 관한 연구 (A Study on the Determination of Vibration Criteria for Vibration Sensitive Equipments Using Impact Test)

  • 이홍기;박해동;김두훈;김사수
    • 소음진동
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    • 제7권2호
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    • pp.247-254
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    • 1997
  • In the case of a precision equipment, it requires a vibration free environment to provide its proper function. Especially, lithography and inspection devices, which have sub-nanometer class high accuracy and resolution, have come to necessity for producing more improved giga class semiconductor wafers. This high technology equipments require very strict environmental vibration standard in proportion to the accuracy of the manufacturing, inspecting devices. The vibration criteria are usually obtained either by the real vibration exciting test on the equipment or by the analytical calculation. This paper proposes a new method to solve this problem at a time. The permissible vibration level to a precision equipment can be easily obtained by analyzing a process of Frequency Response Function. This paper also demonstrates its effectiveness by applying the proposed method to finding the vibration criteria of a Computer Hard Disk Driver by Impact Test.

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반도체용 PCB 기판시스템의 구조해석 (Structural Analysis of a PCB Substrate System for Semiconductor)

  • 임경화;양손;윤종국;김영균;유선중
    • 반도체디스플레이기술학회지
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    • 제10권4호
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    • pp.113-118
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    • 2011
  • According to the high accuracy of semiconductor equipments, PCB substrate with much thin thickness is required. However, it is very difficult to sustain the PCB substrate without deformation in case of horizontal installation, due to low bending stiffness. In this research, new PCB process equipment with vertical installation has been developed in order to solve the problem of PCB substrate damage during etching process. As the main parts of etching system on PCB substrate, PCB substrate and JIG are analyzed through finite element method and experimental test. Through the analysis results of stress state, we could find the optimal JIG design to make the damage as low as possible.

반도체 테스트 소켓의 검사속도 및 반복 정밀도 개선형 검사장치에 관한 연구 (A Study on the Test Device for Improving Test Speed and Repeat Precision of Semiconductor Test Socket)

  • 박형근
    • 한국산학기술학회논문지
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    • 제22권1호
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    • pp.327-332
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    • 2021
  • 패키지레벨에서 반도체의 신뢰성 검사는 테스트 소켓에 반도체 칩 패키지를 탑재시킨 상태에서 테스트가 진행되며, 테스트 소켓은 기본적으로 반도체 칩 패키지의 형태에 따라서 그 모양이 결정되는 것이 일반적이다. 또한, 반도체 칩 패키지의 리드와 소켓 리드의 기계적인 접촉에 의해 테스트 장비와 연결하는 매개체의 역할을 하며, 신호전달 과정에서 신호의 손실을 최소화하여 반도체에 검사신호를 잘 전달할 수 있도록 하는 기능이 핵심이다. 본 연구에서는 이웃하고 있는 전기 전달 경로의 상호 영향성을 검사 할 수 있는 기술을 적용함으로써 수명 검사와 정밀 측정뿐만 아니라 이웃하고 있는 전기 전달 경로의 구조를 포함하여 단 한 번의 접촉을 통해 100개미만의 실리콘 테스트 소켓의 합선 테스트가 가능하도록 개발하였다. 개발된 장치의 테스트 결과 99%이상의 테스트 정밀도와 0.66이하의 동시 검사속도 특성을 나타내었다.

COF(Chip On Film)에서의 Polyimide/Buffer layer/Cu 접착력 향상 (Adhesive improvement of the Polyimide/Buffer layer/Cu at the COF(Chip On Film))

  • 이재원;김상호;이지원;홍순성
    • 반도체디스플레이기술학회지
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    • 제3권3호
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    • pp.11-17
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    • 2004
  • This research has been progressed for adhesive improvement of the Polyimide/Buffer layer/Cu at the COF(Chip On Film) which induced as the alternative plan about high concentration of a circuit or substrates according to demands of miniaturization and high efficiency of various electronic equipment. RF plasma equipment was applied to when plama pretreatment was performed for improvement of adhesive strength of PI and Cr as the buffer layer. Experimental fluents were a species of the buffer layer, depositied time and the ratio of $O_2$/Ar when performed to plasma pretreatment. The results are that Ni was superior to Cr at peel test according to a species of the buffer layer, peel strength and Cu THK were showed proportional relation to deposition structure of the same buffer layer and sample of the Cr depositied time(30 sec) and Cu depositied time(20 min) was showed good adhesion to peel test according to Cr's depositied time and Cu's depositied time. When perform PI's plasma pretreatment peel strength and $O_2$/Ar ratio were showed proportional relation. But $O_2$/Ar(2/5) was best condition since then decreased.

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Efficient Multi-site Testing Using ATE Channel Sharing

  • Eom, Kyoung-Woon;Han, Dong-Kwan;Lee, Yong;Kim, Hak-Song;Kang, Sungho
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제13권3호
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    • pp.259-262
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    • 2013
  • Multi-site testing is considered as a solution to reduce test costs. This paper presents a new channel sharing architecture that enables I/O pins to share automatic test equipment (ATE) channels using simple circuitry such as tri-state buffers, AND gates, and multiple-input signature registers (MISR). The main advantage of the proposed architecture is that it is implemented on probe cards and does not require any additional circuitry on a target device under test (DUT). In addition, the proposed architecture can perform DC parametric testing of the DUT such as leakage testing, even if the different DUTs share the same ATE channels. The simulation results show that the proposed architecture is very efficient and is applicable to both wafer testing and package testing.

반도체 제조 공정에서 장비와 호스트간 SECS 프로토콜 통신을 위한 응용 프로그램 구현 (An Application Implementation for the SECS Protocol Communication between Equipments and a Host in a Semiconductor Process)

  • 김대원;전정만;이병훈;김홍석;이호길
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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    • pp.293-293
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    • 2000
  • The SECS(SEMI Equipment Communications Standard) is a standard protocol for communication between equipments and a host in semiconductor processes. This paper proposes the implementation of the HSMS(High-speed SECS Message Services) as an interface for transmission of the SECS messages and SECS-II containing message contents defined as an SEMI standard. The HSMS driver is implemented as a type of the daemon program and several DLL files. The SECS-II composes of the SML(SECS Message Language) file defining the SECS messages, the SML translator being able to interpret and transform the SML, and the data index table being able to refer to SECS messages. We also define the shared parameter to exchange the HSMS header and SECS message between the HSMS and the SECS-II. Eventually, to show the effectiveness of the proposed drivers, we test the SECS communications between equipments and a host using the implemented communication programs.

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기계학습을 이용한 로봇 관절부 고장진단에 대한 연구 (Study on the Failure Diagnosis of Robot Joints Using Machine Learning)

  • 김미진;구교문;심재홍;김효영;김기현
    • 반도체디스플레이기술학회지
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    • 제22권4호
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    • pp.113-118
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    • 2023
  • Maintenance of semiconductor equipment processes is crucial for the continuous growth of the semiconductor market. The process must always be upheld in optimal condition to ensure a smooth supply of numerous parts. Additionally, it is imperative to monitor the status of the robots that play a central role in the process. Just as many senses of organs judge a person's body condition, robots also have numerous sensors that play a role, and like human joints, they can detect the condition first in the joints, which are the driving parts of the robot. Therefore, a normal state test bed and an abnormal state test bed using an aging reducer were constructed by simulating the joint, which is the driving part of the robot. Various sensors such as vibration, torque, encoder, and temperature were attached to accurately diagnose the robot's failure, and the test bed was built with an integrated system to collect and control data simultaneously in real-time. After configuring the user screen and building a database based on the collected data, the characteristic values of normal and abnormal data were analyzed, and machine learning was performed using the KNN (K-Nearest Neighbors) machine learning algorithm. This approach yielded an impressive 94% accuracy in failure diagnosis, underscoring the reliability of both the test bed and the data it produced.

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