• KIISE Transactions on Computing Practices
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• v.21 no.10
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• pp.645-650
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• 2015

Tester Interface Software (TIS) provides all software functions that are necessary for a testing device to perform the test process on a memory semiconductor package from the time the device is put into the test equipment until the device is discharged from the equipment. TIS should perform the same work over all types of equipment regardless of their tester models. However, TIS has been developed and managed independently of the tester models because there are various equipment and computer models that are used in the test process. Therefore, more maintenance, time and cost are required for development, which adversely affects the quality of the software, and the problem becomes more serious when the new tester model is introduced. In this paper, we propose the Cross-platform Tester Interface Software (CTIS) framework, which can be integrated and operated on heterogeneous equipment and OSs.

• Journal of the Semiconductor & Display Technology
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• v.14 no.4
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• pp.67-71
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• 2015

Product of technology developed in this study is an external interface for controlling the equipment of pendant key remote control system circuit board, and it is used in the electronic component test equipment system. Main control system module is in the role as a device for controlling the various control devices that make up the integrated system for microscopic examination at the request of the host computer engineers to control the inspection equipment. The pentane-key interface module to its role as a device for controlling the various control devices that make up the integrated system for microscopic examination at the request of the host computer for the engineer to control the inspection equipment. Development of the control system can be expected in the configuration of a system for efficient and accurate inspection of high-precision parts.

• Journal of Advanced Navigation Technology
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• v.15 no.6
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• pp.1104-1110
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• 2011

The conventional semiconductor equipment has adopted SRAM module as the test pattern memory, which has a simple design and does not require refreshing. However, SRAM has its disadvantages as it takes up more space as its capacity becomes larger, making it difficult to meet the requirements of large memories and compact size. if DRAM is adopted as the semiconductor inspection equipment, it takes up less space and costs less than SRAM. However, DRAM is also disadvantageous because it requires the memory cell refresh, which is not suitable for the semiconductor examination equipments that require correct timing. Therefore, In this paper, we will proposed an algorithm for punctuality guarantee of memory-free inspection equipment using DDR2 SDRAM. And we will Developed memory controller using punctuality guarantee algorithm. As the results, show that when we adopt the DDR2 SDRAM, we can get the benefits of saving 13.5 times and 5.3 times in cost and space, respectively, compared to the SRAM.

• Journal of the Semiconductor & Display Technology
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• v.8 no.4
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• pp.53-58
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• 2009

A SMT mounter is a kind of equipment that mounts SMD parts quickly on the printed circuit board. By using linear motors, it is controlled with high speed and precision, which is similar to semi-conductor and display process equipment. It is necessarily used in an assembly process of an electronic device. Mobile devices such as a mobile phone and PDA are required to reduce mount areas due to the demands for high performance and small size. Hence, super small sized and complex mobile devices have been developed. To improve the productivity of the corresponding equipment, designs with large sized, high speed, and multidisciplinary functions have been consistently performed. Meanwhile, a design trend of large size and light-weight on SMT mounter causes a low natural frequency of systems and vibration problems at the high speed operation. In this paper, the dynamic characteristics of the SMD mounter system were investigated through a modal test and transmissibility test, and verified by finite element method. Also, various design improvement was performed to avoid the resonance phenomena.

• Journal of the Semiconductor & Display Technology
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• v.2 no.2
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• pp.25-30
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• 2003

In the case of a vibration sensitive equipment, it require a vibration free environment to provide its proper function. Especially, lithography and inspection device, which have sub-nanometer class high accuracy and resolution, have come to necessity for producing more improved Giga Class semi conductor wafers. This high technology equipments require very strict environmental vibration criteria in proportion to the accuracy of the manufacturing. In this paper, the dynamic analysis and modal test were performed to evaluate the dynamic properties of the constructing clean room structure. Based on these results, a structural dynamic modification(SDM) were required to satisfiy the vibration allowable limit for pression machine. Therefore, in order to improve the dynamic stiffness of clean room structure, the VSD system which can control the force applied on structure, were adopted and its utility were proved from dynamic test results of the improved structure after a modification work.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.39 no.1
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• pp.153-161
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• 2016

Semiconductor manufacturing has suffered from the complex process behavior of the technology oriented control in the production line. While the technological processes are in charge of the quality and the yield of the product, the operational management is also critical for the productivity of the manufacturing line. The fabrication line in the semiconductor manufacturing is considered as the most complex part because of various kinds of the equipment, re-entrant process routing and various product devices. The efficiency and the productivity of the fabrication line may give a significant impact on the subsequent processes such as the probe line, the assembly line and final test line. In the management of the re-entrant process such as semiconductor fabrication, it is important to keep balanced fabrication line. The Performance measures in the fabrication line are throughput, cycle time, inventory, shortage, etc. In the fabrication, throughput and cycle time are the conflicting performance measures. It is very difficult to achieve two conflicting goal simultaneously in the manufacturing line. The capacity of equipment is important factor in the production planning and scheduling. The production planning consideration of capacity can make the scheduling more realistic. In this paper, an input and scheduling rule are to achieve the balanced operation in semiconductor fabrication line through equipment capacity and workload are proposed and evaluated. New backward projection and scheduling rule consideration of facility capacity are suggested. Scheduling wafers on the appropriate facilities are controlled by available capacity, which are determined by the workload in terms of the meet the production target.

• Journal of the Korean Institute of Intelligent Systems
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• v.22 no.6
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• pp.694-699
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• 2012

In this paper, semiconductor package inspection results using white light interferometer with large F.O.V., in order to apply semiconductor product inspection process, are shown. Experimental 3D data repeatability test results for the same special bumps of each substrate are shown. Experimental 3D data repeatability test results for all the bumps in each substrate are also shown. Semiconductor package inspection using white light interferometer with large F.O.V. is very important for the fast 3D data inspection in semiconductor product inspection process. This paper is surely helpful for the development of in-line type fast 3D data inspection machine.

• IE interfaces
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• v.18 no.3
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• pp.350-360
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• 2005

This paper considers a strategy for planning of rework in semiconductor monitoring burn-in test process. The equipment error in monitoring burn-in test process generates many defects. These defects are transformed into good products by rework process, i.e. retest. Rework has the advantage of saving production costs. But rework increases holding costs and incurs rework costs. In monitoring burn-in test process, rework depends on operator's experience with no pre-defined specification. In practice, a number of rework activities are performed with respect to the product importance and inventory quantity. Moreover, disregard for order jobs schedule have caused due date penalties. So a strategy for planning of rework by which order jobs schedule are not affected is suggested. Futhermore, production costs, rework costs and inventory costs for planning of rework are considered.

• Journal of the Korean Society of Safety
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• v.17 no.4
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• pp.94-100
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• 2002

As the use of automatic handling equipment for sensitive semiconductor devices is rapidly increased, manufacturers of electronic components and equipments need to be more alert to the problem of electrostatic discharges(ESD). In order to analyze damage characteristics of semiconductor device damaged by ESD, this study adopts a new charged-device model(CDM), field-induced charged model(FCDM) simulator that is suitable for rapid, routine testing of semiconductor devices and provides a fast and inexpensive test that faithfully represents ESD hazards in plants. High voltage applied to the device under test is raised by the field of non-contacting electrodes in the FCDM simulator, which avoids premature device stressing and permits a faster test cycle. Discharge current and time are measured and calculated. The characteristics of electrostatic attenuation of domestic semiconductor devices are investigated to evaluate the ESD phenomena in the semiconductors. Also, the field charging mechanism, the device thresholds and failure modes are investigated and analyzed. The damaged devices obtained in the simulator are analyzed and evaluated by SEM. The results obtained in this paper can be used to prevent semiconductor devices form ESD hazards and be a foundation of research area and industry relevant to ESD phenomena.

• Journal of the Korean Society of Safety
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• v.15 no.4
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• pp.62-68
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• 2000

Static electricity in electronics manufacturing plants causes the economic loss, yet it is one of the least understood and least recognized effects haunting the industry today. Today's challenge in semiconductor devices is to achieve greater functional density pattern and to miniaturize electronic systems of being more fragile by electrostatic discharges(ESD) phenomena. As the use of automatic handling equipment for static-sensitive semiconductor components is rapidly increased, most manufacturers need to be more alert to the problem of ESD. One of the most common causes of electrostatic damage is the direct transfer of electrostatic charge from the human body or a charged material to the static-sensitive devices. To evaluate the ESD hazards by charged human body and devices, in this paper, characteristics of electrostatic attenuation in domestic semiconductor devices is investigated and the voltage to cause electronic component failures is investigated by field-induced charged device model(FCDM) tester. The FCDM simulator provides a fast and inexpensive test that faithfully represents ESD hazards in plants. Also the results obtained in this paper can be used for the prevention of semiconductor failure from ESD hazards.