• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.367-368
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• 2014

This paper investigates characteristics of high power semiconductor device losses in 5MW-class Permanent Magnet Synchronous Generator (PMSG) Medium Voltage (MV) wind turbines. High power semiconductor device of press-pack type IGCT of 6.5kV is considered in this paper. Analysis is performed based on neutral point clamped (NPC) 3-level back-to-back type voltage source converter (VSC) supplied from grid voltage of 4160V. This paper describes total loss distribution at worst case under inverter and rectifier operating mode for the power semiconductor switches. The loss analysis is confirmed through PLECS simulations. In addition, the loss factors due to di/dt snubber and ac input filter are presented. The investigation result shows that IGCT type semiconductor devices generate the total efficiency of 97.74% under the rated condition.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.412-414
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• 1994

A new active resonant snubber (ARS) circuit providing the ideal switching conditions for PWM converter is presented. By using the proposed ARS circuit to PWM converters, the power switches can be operated to give zero-current and zero-voltage at both the instant of switch off and switch on, without increasing voltage/current stresses of the switches. Furthermore, the PWM converters employed ARS circuit has the advantage that it can operate at constant frequency, giving better definded EMI and filter ripple, and it is also suited for high-power application regardless of the semiconductor devices (such as MOSFETs or IGBTs) used as a power switches.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1610-1620
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• 2015

A major problem in conventional multilevel inverter is that an increase in power semiconductor switches causes an increase in cost and switching losses of the inverter. The multicarrier strategy adopted for the multilevel inverters has become more popular due to reduced cost, lower harmonic distortion, and higher voltage capability than the conventional switching strategy applied to inverters. Various topologies and modulation strategies have been reported for utility and drive applications. Level shifted based pulse width modulation techniques are proposed to investigate the performance of the multilevel inverter. The proposed work focuses on reducing the utilized switches so that the cost and the switching losses of the inverter do not go up and the consistent efficiency could be achieved. This paper presents the detailed analysis of these topologies. The analysis is based on the number of switches, DC sources, output level, maximum voltage, and the efficiency. As an illustration, single phase cascaded multilevel inverter topologies are simulated using MATLAB/SIMULINK and the experimental results demonstrate the viability of these inverters.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.809-812
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• 2002

This paper presents the structures for a CPW shunt RF switch using MEMS(Micro Electro Mechanical System). Recent development in MEMS technology has made the design and fabrication of micro-mechanical switches as new switching elements. The micro-mechanical switches have low insertion loss, negligible power consumption, and good isolation compared to semiconductor switches. The fabricated structure shows an insertion loss of 2dB at 20GHz When a bias voltages of 12V is apply.

• Proceedings of the KIEE Conference
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• 2000.07e
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• pp.157-161
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• 2000

The electronic ballasts for low pressure discharge lamps are produced and commercialized. However, the electronic ballasts for high pressure lamps are now in progress because of poor reliability and high cost. The major case of troubles with electronic ballasts are thermal destruction of semiconductor output switches due to non ideal i-v characteristics of switch. The loss converts to heat and rises the temperature of switch and it increases proportionally to switching frequency and value of current and voltage. This study shows the variable frequency ballasts which can suppress the heating of switches efficiently. It is used for the limitation the switch current and the rising temperature of switch by impedance variation of lamp inductor. As a result, initial warm-up time of the proposed ballasts was faster than that of magnetic ballasts about 90 msec. Power factor of tested ballasts follow as ; input and output average of magnetic ballasts are 93 [%] and 86 [%], respectively, And proposed ballasts are 97 [%] and 99 [%], respectively.

• Proceedings of the KIEE Conference
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• 2002.04a
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• pp.213-215
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• 2002

This paper presents grid connected photovoltaic inverter system using a new Zero-Current-Transition(ZCT) technique. The main switches of the proposed grid connected inverter are turned off under the zero current condition by operating the auxiliary circuit and also all semiconductor devices, switches and diodes, are applied to low rated voltage regardless of the load condition. In additionally, the proposed ZCT scheme has advantages, which are without the additional current stresses and the conduction losses on the main switches during the resonance period of the auxiliary circuit. The simulation was performed to verify the validity of the proposed grid connected photovoltaic ZCT inverter system.

• Journal of Power Electronics
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• v.11 no.6
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• pp.787-792
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• 2011

In this paper, a new three phase soft switching inverter is presented. All of the semiconductor elements of this converter are soft switched. Employing only two auxiliary switches as DC-link switches and a simple control circuit are the advantages of the proposed inverter. The analytical equations and operating modes of the presented inverter are explained in details. The design considerations are presented and the experimental results verify the theoretical analysis.

• Journal of Power Electronics
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• v.12 no.5
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• pp.723-730
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• 2012

This paper presents a new ZVS single phase bridgeless (Power Factor Correction) PFC, using an active clamp to achieve zero-voltage-switching for all main switches and diodes. Since the presented PFC uses a bridgeless rectifier, most of the time, only two semiconductor components are in the main current path, instead of three in conventional single-switch configurations. This property significantly reduces the conduction losses,. Moreover, zero voltage switching removes switching loss of all main switches and diodes. Also, auxiliary switch turns on zero current condition. The presented converter needs just a simple non-isolated gate drive circuitry to drive all switches. The eight stages of each switching period and the design considerations and a control strategy are explained. Finally, the converter operation is verified by simulation and experimental results.

• Journal of Power Electronics
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• v.15 no.4
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• pp.951-963
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• 2015

In this paper, a new symmetric multilevel inverter is proposed. A simple structure for the cascaded multilevel inverter topology is also proposed, which produces a high number of levels with the application of few power electronic devices. The symmetric multilevel inverter can generate 2n+1 levels with a reduced number of power switches. The basic unit is composed of a single and double source unit (SDS-unit). The application of this SDS-unit is for reducing the number of power electronic components like insulated gate bipolar transistors, freewheeling diodes, gate driver circuits, dc voltage sources, and blocked voltages by switches. Various new algorithms are recommended to determine the magnitude of dc sources in a cascaded structure. Furthermore, the proposed topology is optimized for different goals. The proposed cascaded structure is compared with other similar topologies. For verifying the performance of the proposed basic symmetric and cascaded structure, results from a computer-based MATLAB/Simulink simulation and from experimental hardware are also discussed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.4
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• pp.218-221
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• 2015

Power MOSFETs (metal oxide semiconductor field effect transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. In this study we have investigated a structure to reduce the on-resistance characteristics of the MOSFET. We have a proposed MOSFET structure of active cells region buried under the gate pad. The measurement are carried out with a EDS to analyze electrical characteristics, and the proposed MOSFET are compared with the conventional MOSFET. The result of proposed MOSFET was 1.68[${\Omega}$], showing 10% improvement compared to the conventional MOSFET at 700[V].