• The Journal of the Korea Contents Association
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• v.10 no.4
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• pp.386-396
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• 2010

The purpose of this study is to examine the non-regular labor dispute from beginning to the ends, thus, give guidance for future similar labor disputes. As a result of this study, firstly, subcontract company union negotiated with their companies, but after their companies was shut up, the union demanded negotiation with Hynix Co.(Hynix Co. contracted with union member's companies about cleaning job etc for every year). However, Hynix rejected the union's demand, because Hynix Co. do not have the legal obligation to negotiate with subcontract company union. Secondly, union members was to in unemployment and for the employment & negotiation with Hynix Co. they did illegal actions against Hynix Co. Thirdly, there was tried many efforts by NGO & government authorities etc to settle the disputes, and mediated, arbitrated by private expert(Certified Public Labor Attorney) Finally, both parties(that is Hynix Co. and subcontract company union) negotiated each other and settled the dispute without employment.

• Proceedings of the Korean Vacuum Society Conference
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• 1998.02a
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• pp.20-20
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• 1998

I Ion beam technology has recently attracted much interest because it has exciting t technological p아:ential for surface analysis, ion beam mixing, surface cleaning and etching i in thin film growth and semiconductor fabrication processes, etc. Es야~cially, ion beam s sputtering has been widely used for sputter depth profiling with x-photoelectron S spectroscopy (XPS) , Auger electron s$\pi$~troscopy(AES), and secondary-ion mass S야i따oscopy(SIMS). However, The problem of surface compositional ch없1ge due to ion b bombardment remains to be understo여 없ld solved. So far sputtering processes have been s studied by s따face an외ysis tools such as XPS, AES, and SIMS which use the sputtering p process again. It would be improbable to measure the modified surface composition profiles a accurately due to ion beam bombardment with surface analysis techniques based on sputter d depth profiling. However, recently Medium energy ion scattering spectroscopy(MEIS) has b been applied to study the sputtering of solid surface at ion bombardment and has been p proved that it has been extremely valuable in probing the surface composition 뻐d s structure nondestructively and quantita디vely with less than 1.0 nm depth resolution. To u understand the sputtering processes of solid surface at ion bombardment, The Molecular D Dynamics(MD) and Monte Carlo(MC) simulation has been used and give an intimate i insight into the sputtering processes of solid surfaces. In this presentation, the sputtering processes of alloys and compound samples at ion b bombardment will be reviewed and the MEIS results for the Ar+ sputter induced altered l layer of the TazOs thin film 뻐dd없nage profiling of Ar+ ion sputt얹"ed Si(100) surface will b be discussed with the results of MD and MC simulation.tion.

• Korean Chemical Engineering Research
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• v.49 no.4
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• pp.485-490
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• 2011

Tetrafluoromethane($CF_4$) has been used as etching and chamber cleaning gases for semiconductor manufacturing processes. These gases need to be removed efficiently because of their strong absorption of infrared radiation and long atmospheric lifetime which causes the global warming effect. We have developed a waterjet gliding arc plasma system in which plasma is combined with waterjet and investigated optimum operating conditions for efficient $CF_4$ destruction through enlarging discharge region and producing large amount of OH radicals. The operating conditions are waterjet flow rate, initial $CF_4$ concentration, total gas flow rate, specific energy input. Through the parametric studies, the highest $CF_4$ destruction of 97% was achieved at 2.2% $CF_4$, 7.2 kJ/L SEI, 9 L/min total gas flow rate and 25.5 mL/min waterjet flow rate.

• Journal of Surface Science and Engineering
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• v.32 no.3
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• pp.239-243
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• 1999

At Present, 200mm wafer technology is being applied for commercial fabrications of 64, 128, and 256 M DRAM devices, and 300mm technology will be evolved for 1G DRAM devices in the early 21th century, recognizing limitations of several process technologies. In particular recognition has been realized in harmful effects of surface contamination of trace metals introduced during devicing processes. Such a guide line for surface metal contamination has been proposed as 1E9 and 1E10 atoms/$\textrm{cm}^2$ of individual metal contamination for wafering and devicing of 1G DRAM, respectively, and so its measurement limit should be at least 1E8 atoms/$\textrm{cm}^2$. The detection limit of present measurement systems is 2E9 atoms/$\textrm{cm}^2$ obtainable with TRXFA(Total Reflection X-Ray Fluorescence Analysis). TRXFA is nondestructive and the simplest in terms of operation, and it maps the whole wafer surfaces but needs detection improvement. X-Ray intensity produced with synchrotron accelerator is much higher than that of conventional X-ray sources by order of 4-5 magnitudes. Hence theoretically its reactivity with silicon surfaces is expected to be much higher than the conventional one, realizing improvement of detection limit. X-ray produced with synchrotron accelerator is illuminated at a very low angle with silicon wafer surfaces such as 0.1 degree and reflects totally. Hence informations only from surface can be collected and utilized without overlapping with bulk informations. This study shows the total reflection phenomenon and quantitative improvement of detection limit for metallic contamination. It is confirmed that synchrotron X-ray can be a very promising alternative for realizing improvement of detection limit for the next generation devices.

• Tribology and Lubricants
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• v.35 no.5
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• pp.274-285
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• 2019

Chemical mechanical polishing (CMP), which is a material removal process involving chemical surface reactions and mechanical abrasive action, is an essential manufacturing process for obtaining high-quality semiconductor surfaces with ultrahigh precision features. Recent rapid growth in the industries of digital devices and semiconductors has accelerated the demands for processing of various substrate and film materials. In addition, to solve many issues and challenges related to high integration such as micro-defects, non-uniformity, and post-process cleaning, it has become increasingly necessary to approach and understand the processing mechanisms for various substrate materials and abrasive particle behaviors from a tribological point of view. Based on these backgrounds, we review recent CMP R&D trends in this study. We examine experimental and analytical studies with a focus on substrate materials and abrasive particles. For the reduction of micro-scratch generation, understanding the correlation between friction and the generation mechanism by abrasive particle behaviors is critical. Furthermore, the contact stiffness at the wafer-particle (slurry)-pad interface should be carefully considered. Regarding substrate materials, recent research trends and technologies have been introduced that focus on sapphire (${\alpha}$-alumina, $Al_2O_3$), silicon carbide (SiC), and gallium nitride (GaN), which are used for organic light emitting devices. High-speed processing technology that does not generate surface defects should be developed for low-cost production of various substrates. For this purpose, effective methods for reducing and removing surface residues and deformed layers should be explored through tribological approaches. Finally, we present future challenges and issues related to the CMP process from a tribological perspective.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.1
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• pp.603-608
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• 2018

Although the voltage-applied discharge method is most widely used in the semiconductor and display industries, periodic management costs are incurred because the method causes defects due to the absorption of ambient fine dust and causes emitter tip contamination due to the discharge. The emitter tip contamination problem is caused by the accumulation of fine particles in ambient air due to the corona discharge of the ionizer. Fuzzy ball generation accelerates the wear of the emitter tip and deteriorates the performance of the ionizer. Although a mechanical cleaning method using a manual brush or an automatic brush is effective for contaminant removal, it requires management of additional mechanical parts by the user. In some cases, contaminants accumulated in the emitter may be transferred to the wafer or product. In order to solve this problem, we developed an ionizer for a clean environment that can remove the pencil-type emitter tip and directly ionize the surrounding gas molecules using the tungsten wire located inside the ion tank. As a result of testing and certification by the Korea Institute of Machinery and Materials, the average concentration was $0.7572particles/ft^3$, the decay time was less than two seconds, and the ion valance was 7.6 V, which is satisfactory.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.150.1-150.1
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• 2014

Showerhead is used as a main part in the semiconductor equipment. The face plate flatness should remain constant and the cleaning performance must be gained to keep the uniformity level of etching or deposition in chemical vapor deposition process. High operating temperature or long period of thermal loading could lead the showerhead to be deformed thermally. In some case, the thermal deformation appears very sensitive to showerhead performance. This paper describes the methods for robust design using computational fluid dynamics. To reveal the influence of the post distribution on flow pattern in the showerhead cavity, numerical simulation was performed for several post distributions. The flow structure appears similar to an impinging flow near a centered baffle in showerhead cavity. We took the structure as an index to estimate diffusion path. A robust design to reduce the thermal deformation of showerhead can be achieved using post number increase without ill effect on flow. To prevent the showerhead deformation by heat loading, its face plate thickness was determined additionally using numerical simulation. The face plate has thousands of impinging holes. The design key is to keep pressure drop distribution on the showerhead face plate with the holes. This study reads the methodology to apply to a showerhead hole design. A Hagen-Poiseuille equation gives the pressure drop in a fluid flowing through such hole. The assumptions of the equation are the fluid is viscous-incompressible and the flow is laminar fully developed in a through hole. An equation can be expressed with radius R and length L related to the volume flow rate Q from the Hagen-Poiseuille equation, $Q={\pi}R4{\Delta}p/8{\mu}L$, where ${\mu}$ is the viscosity and ${\Delta}p$ is the pressure drop. In present case, each hole has steps at both the inlet and the outlet, and the fluid appears compressible. So we simplify the equation as $Q=C(R,L){\Delta}p$. A series of performance curves for a through hole with geometric parameters were obtained using two-dimensional numerical simulation. We obtained a relation between the hole diameter and hole length from the test cases to determine hole diameter at fixed hole length. A numerical simulation has been performed as a tool for enhancing showerhead robust design from flow structure. Geometric parameters for the design were post distribution and face plate thickness. The reinforced showerhead has been installed and its effective deposition profile is being shown in factory.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.1-7
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• 1999

We developed Fabrication process of embedded passive components in MCM-D substrate. The proposed MCM-D substrate is based on Cu/photosensitive BCB multilayer. The substrate used is Si wafer and Ti/cu metallization is used to form the interconnect layer. Interconnect layers are formed with 1000$\AA$ Ti/3000$\AA$ Cu by sputtering method and 3$\mu\textrm{m}$ Cu by electrical plating method. In order to form the vias in photosensitive BCB layer, the process of BCB and plasma etch using $C_2F_6$ gas were evaluated. The MCM-D substrate is composed of 5 dielectric layers and 4 interconnect layers. Embedded resistors are made with NiCr and implemented on the $2^{nd}$ dielectric layer. The sheet resistance of NiCr is controlled to be about 21 $\Omega$/sq at the thickness of 600$\AA$. The multi-turn sprial inductors are designed in coplanar fashion on the $4^{th}$ interconnect layer with an underpass from the center to outside using the lower $3^{rd}$ interconnect layer. Capacitors are designed and realized between $1^{st}$ interconnect layer and $2^{nd}$ interconnect layer. An important issue in capacitor is the accurate determination of the dielectric thickness. We use the 900$\AA$ thickness of PECVD silicon nitride film as dielectric. Capacitance per unit area is about 88nF/$\textrm {cm}^2$at the thickness of 900$\AA$. The advantage of this integration process is the compatibility with the conventional semiconductor process due to low temperature PECVD silicon nitride process and thermal evaporation NiCr process.

• Journal of Korean Society of Occupational and Environmental Hygiene
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• v.34 no.1
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• pp.18-25
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• 2024

Objectives: The primary aim of this study is to create an Occupational Safety and Health (OSH) guide for high-risk maintenance tasks, specifically one designed for maintenance work (MW) in the electronics industry. Methods: The methodology involved a literature review, field investigations, and discussions. An initial draft of the OSH guide was created and then refined through consultations with experts possessing extensive experience in MW for electronic processes. Results: Specific MW tasks within electronics processing facilities identified as high-risk by the research were selected. A comprehensive OSH guide for these tasks was developed consisting of approximately 11 to 12 components and encompassing about 20-25 pages. Implementing safety and health measures before, during, and after MW is crucial for the protection of maintenance personnel. The guide is enriched with real-case scenarios of industrial accidents and occupational diseases to enhance maintenance workers' comprehension of the OSH principles. For a clearer understanding of and adherence to the safety protocols, the guide incorporates visual aids, including cartoons and photographs. Conclusions: This OSH guide is designed to ensure the protection of workers involved in maintenance activities in the electronics industry. It aligns with global standards set by the International Organization for Standardization (ISO) and Semiconductor Equipment and Material International (SEMI) to ensure a high level of safety and compliance.