• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1959-1960
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• 2008

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the algorithm that it also suggest algorithm that reduce additional circuits and time delay as matching of pattern about 2-type circuits which are CUT(circuit Under Test) and additional circuits so that the designer can detect the wrong location in CUT: Circuit Under Test.

• 대한산업공학회지
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• 제40권3호
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• pp.257-266
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• 2014

The semiconductor manufacturing industry is managed by a number of parameters from the FAB which is the initial step of production to package test which is the final step of production. Various methods for prediction for the quality and yield are required to reduce the production costs caused by a complicated manufacturing process. In order to increase the accuracy of quality prediction, we have to extract the significant features from the large amount of data. In this study, we propose the method for extracting feature from the cell level data of probe test process using OPTICS which is one of the density-based clustering to improve the prediction accuracy of the quality of the assembled chips that will be placed in a package test. Two features extracted by using OPTICS are used as input variables of quality prediction model because of having position information of the cell defect. The package test progress for chips classified to the correct quality grade by performing the improved prediction method is expected to bring the effect of reducing production costs.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권4호
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• pp.199-203
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• 2006

This paper presents an ASER (Accelerated Soft Error Rate) integral model. The model is based on the facts that the generated EHP/s(electron hole pairs) are diminished after some residual range of the incident alpha particle, where residual range is a function of the incident angle and the capping layer thickness over the semiconductor junction. The ASER is influenced by the flux of the alpha particles, the junction area ratio, the alpha particle incident angle when the critical charge is same as the collected charge, and the sizes of the alpha source and the chip. The model was examined with 8M static RAM samples. The measured ASER data showed good agreement with the calculated values using the model. The ASER decreased exponentially with respect to the operational voltage. As the capping layer thickness increases up to $16{\mu}m$, the ASER increases, and after that thickness, the ASER decreases. The ASER increased as the depth of BNW increased from $0{\mu}m\;to\;4{\mu}m$. and then saturated. The ASER decreased as the node capacitance increased from 2fF to 5fF.

• 한국정밀공학회지
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• 제22권7호
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• pp.27-37
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• 2005

Direct writing technology on the silicon wafer surface is used to reduce the size of the chip as the miniature trend in electronic circuit. In order to improve the productivity and efficiency, the real time quality estimation is very important in each semiconductor process. In laser marking, marking quality is determined by readability which is dependant on the contrast of surface, the line width, and the melting depth. Many researchers have tried to find theoretical and numerical estimation models fur groove geometry. However, these models are limited to be applied to the real system. In this study, the estimation system for the line width during the laser marking was proposed by process monitoring method. The light intensity emitted by plasma which is produced when irradiating the laser to the silicon wafer was measured using the optical sensor. Because the laser marking is too fast to measure with external sensor, we build up the coaxial monitoring system. Analysis for the correlation between the acquired signals and the line width according to the change of laser power was carried out. Also, we developed the models enabling the estimation of line width of the laser marking through the statistical regression models and may see that their estimating performances were excellent.

• 한국통신학회논문지
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• 제25권1B호
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• pp.175-182
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• 2000

적외선을 이용한 수/발광 다이오드에 집적소자를 혼합한 Hybrid형 단거리 광무선 통신용 원칩모듈을 개발하였다. 발광다이오드는 850nm 의 적외선파장을 30$^{\circ}$지향각을 갖는 AlGaAs계 고속신호용으로서 전파지연이 60 ns 이며, PIN 포토다이오드는 Si계 반도체 수광소자로써 450-1050nm의 파장대에서 수광 흡수율이 양호하고 필터겸용 블록 에포시렌즈를 750nm 파장 저역대를 여과시켰다. 데이터 전송속도는 115.2 kbps이며 IrDA1.0 SIR 표준조건에서 동작이 양호함을 확인하였다.

• 센서학회지
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• 제14권3호
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• pp.137-143
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• 2005

Research in the field of biosensor has enormously increased over the recent years. The metal-oxide semiconductor field effect transistor (MOSFET) type protein sensor offers a lot of potential advantages such as small size and weight, the possibility of automatic packaging at wafer level, on-chip integration of biosensor arrays, and the label-free molecular detection. We fabricated MOSFET protein sensor and proposed the gold-black electrode as the gate metal to improve the response. The experimental results showed that the output voltage of MOSFET protein sensor was varied by concentration of albumin proteins and the gold-black gate increased the response up to maximum 13 % because it has the larger surface area than that of planar-gold gate. It means that the expanded gate allows a larger number of ligands on same area, and makes the more albumin proteins adsorbed on gate receptor.

• 센서학회지
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• 제23권2호
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• pp.87-93
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• 2014

In this paper, we propose a block-based low-power complementary metal oxide semiconductor (CMOS) image sensor (CIS) with a simple pixel structure for power efficiency. This method, which uses an additional computation circuit, makes it possible to reduce the power consumption of the pixel array. In addition, the computation circuit for a block-based CIS is very flexible for various types of pixel structures. The proposed CIS was designed and fabricated using a standard CMOS 0.18 ${\mu}m$ process, and the performance of the fabricated chip was evaluated. From a resultant image, the proposed block-based CIS can calculate a differing contrast in the block and control the operating voltage of the unit blocks. Finally, we confirmed that the power consumption in the proposed CIS with a simple pixel structure can be reduced.

• 한국신뢰성학회지:신뢰성응용연구
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• 제7권1호
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• pp.23-29
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• 2007

Probe card is a test component which is to classify the known good die with electrical contact before the packaging in the ATE (automatic testing equipment). Conventional probe tip was mostly needle type, it has been difficult to meet with conventional type, because of decreasing chip size, pad to pad pitch and pads size increasingly. For that reason, probe cards using MEMS (micro electro mechanical system) technology have been developed for various semiconductor chips. In this paper, Area Array type MEMS Probe tip was designed,, fabricated, and characterized its mechanical and electrical properties. The authors found that good electrical characteristics under $1{\Omega}$ were acquired with gold (Au) and aluminium (Al) pad contact test over 0.5gf and 4gf respectively. And, contact resistance variation under $0.1{\Omega}$ were achieved with 100,000 times of repetition test. And, insertion loss (IS) for high frequency operation was ascertained over 300MHz at -3dB loss.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권1호
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• pp.14-21
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• 2009

A digital differential transmitter based on CMOS inverter worked up to 2.8 Gbps at the supply voltage of 1 V with a $0.18{\mu}m$ CMOS process. By calibrating the output impedance of the transmitter, the impedance matching between the transmitter output and the transmission line is achieved. The PVT variations of pre-driver are compensated by the calibration of the rising-edge delay and falling-edge delay of the pre-driver outputs. The chip fabricated with a $0.18{\mu}m$ CMOS process, which uses the standard supply voltage of 1.8 V, gives the highest data rate of 4Gbps at the supply voltage of 1.2 V. The proposed calibration schemes improve the eye opening with the voltage margin by 200% and the timing margin by 30%, at 2.8 Gbps and 1 V.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권3호
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• pp.166-176
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• 2007

Radio frequency (RF) microelectromechanical systems (MEMS) have been pursued for more than a decade as a solution of high-performance on-chip fixed, tunable and reconfigurable circuits. This paper reviews our research work on RF MEMS switches and switching circuits in the past five years. The research work first concentrates on the development of lateral DC-contact switches and capacitive shunt switches. Low insertion loss, high isolation and wide frequency band have been achieved for the two types of switches; then the switches have been integrated with transmission lines to achieve different switching circuits, such as single-pole-multi-throw (SPMT) switching circuits, tunable band-pass filter, tunable band-stop filter and reconfigurable filter circuits. Substrate transfer process and surface planarization process are used to fabricate the above mentioned devices and circuits. The advantages of these two fabrication processes provide great flexibility in developing different types of RF MEMS switches and circuits. The ultimate target is to produce more powerful and sophisticated wireless appliances operating in handsets, base stations, and satellites with low power consumption and cost.