• Journal of Korean Institute of Industrial Engineers
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• v.29 no.2
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• Journal of the Korean Society for Nondestructive Testing
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• v.21 no.6
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• pp.598-606
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• 2001

Recently, semiconductor packages trend to be thinner, which makes difficult to detect defects therein. A preconditioning test is generally performed to evaluate the reliability of semiconductor packages. The test procedure includes two scanning acoustic microscope (SAM) tests at the beginning and end of the entire test, in order to help detect physical defects such as delaminations and package cracks. In particular, of primary concern are package cracks and delaminations caused by moisture absorbed under ambient conditions. This paper discusses the failure mechanism associated with the moisture absorbed and encapsulated in semiconductors, and the use SAM to detect failures such as tracks and delaminations grown during the preconditioning test.

• Journal of the Korean Society for Nondestructive Testing
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• v.10 no.2
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• pp.43-49
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• 1990

Ultrasonic testing is one of the most useful NDT method for detection of microdefect in the opaque materials. Recently, many applications of the ultrasonic techniques have been extended widely in the new field like electron is and advanced materials. From the result of the experiment, we have hardly found out a crack in the internal parts of the resin and a delamination between chip and resin because of poor performance of the system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.259-262
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• 2013

Multi-site testing is considered as a solution to reduce test costs. This paper presents a new channel sharing architecture that enables I/O pins to share automatic test equipment (ATE) channels using simple circuitry such as tri-state buffers, AND gates, and multiple-input signature registers (MISR). The main advantage of the proposed architecture is that it is implemented on probe cards and does not require any additional circuitry on a target device under test (DUT). In addition, the proposed architecture can perform DC parametric testing of the DUT such as leakage testing, even if the different DUTs share the same ATE channels. The simulation results show that the proposed architecture is very efficient and is applicable to both wafer testing and package testing.

• Journal of the Semiconductor & Display Technology
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• v.3 no.2
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• pp.27-33
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• 2004

This paper is concerned with development of a micro tensile testing machine for optical functional materials such as single or poly crystal silicon and nickel film. Two micro tensile testers have been developed for various types of materials and dimensions. One of the testers is actuated by a PZT and the other is actuated by a servo motor for a precise displacement control. The specifications of PZT actuated micro tensile tester developed are as follows: the volumetric size of tester is desktop sized of 710$\times$200$\times$270 $mm^3$; the minimum load capacity and the load resolution in the load cell of 1N are 3 mN and 0.1 mN respectively; the full stroke and the stoke resolution of piezoelectric actuator are 1 mm and 10nm respectively. A special automatic specimen installing equipment is applied in order to prevent unexpected deformation and misalignment of specimens during handling of specimen for testing.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2659-2661
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• 1999

This paper studies the scope and object of international standards related to power supplies and semiconductor convertors. IEC 60478 and IEC 60686 are international standards for stabilized power supplies with DC and AC output, respectively, and IEC 61204 for low-voltage power supply devices with DC output. IEC 60146 : Semiconductor Convertors is a representative international standard in the field of semiconductor convertors. In this field, there are some international standards such as IEC 60971. IEC 61136-1. IEC 61800. and etc.. In this paper, IEC 60686, 60971, 61136-1, and 61240 are mainly studied.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.114-126
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• 2013

In this paper, we present a set of methodologies to model the electromagnetic susceptibility (EMS) testing of I/O buffers for mobile system memory based on the bulk current injection (BCI) method. An efficient equivalent circuit model is developed for the current injection probe, line impedance stabilization network (LISN), printed circuit board (PCB), and package. The simulation results show good correlation with the measurements and thus, the work presented here will enable electromagnetic susceptibility analysis at the integrated circuit (IC) design stage.

• Proceedings of the Korea Information Processing Society Conference
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• 2024.05a
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• pp.271-274
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• 2024

Fuzzing is widely used as a testing tool to identify vulnerabilities in software programs. Although AFL++ has emerged to facilitate the integration and development of many fuzzers, there are still numerous advance fuzzing technologies that have not yet been incorporated. Among these, we have integrated state-of-the-art directed-based fuzzing techniques into AFL++ to operate in QEMU mode.

• Journal of the Korean Society for Precision Engineering
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• v.10 no.3
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• pp.182-190
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• 1993

In manufacturing process of semiconductor package, the thermal stress owing to high temperature in moulding and the bubbles generated in chip bonding process become main causes to produce void. On this study we evaluated quantitatively void size by use of ultrasonic spectroscopy method which analyze the reflective pulses with broad band frequency in frequency domain, and after destructive testing we verified effectiv- eness of sizing void by use of ultasonic spectroscopy.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.860-863
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• 2003

In this paper high power SMU(Source Measurement Unit) having 50V/1.5A source/measure range has been designed and implemented. The SMU has two operation mode, voltage mode and current mode. The SMU can be used as variable voltage source, variable current source, voltage meter, or current meter. Combining two different unit, output power can be doubled as 100V/1.5A. The developed SMU tan be used many semiconductor testing system and electronic device inspecting system.