• Title/Summary/Keyword: Semiconductor Production Line

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Area Usage Factor Analyzing Method for Semi-conductor Manufacturing Process

  • Konishi, Katunobu;Ukida, Hiroyuki;Sawada, Koutarou
    • 제어로봇시스템학회:학술대회논문집
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    • 1998.10a
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    • pp.480-483
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    • 1998
  • For memory products, it is very important to develop a new production line as soon as possible. All products are inspected to get rid of defected products at the last testing stage. Those inspection data are called FCM. In this paper, based on the FCM data, Area Usage Factor (AUF) analyzing method will be proposed. Process engineers can make up their mind to which direction they should concentrate their analyzing power.

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An Experimental Study on the Drying and Curing Characteristics of Conductive metallic ink using Combined IR and Hot Air Type in the Roll-to-Roll System (R2R 공정에서 적외선가열과 열풍을 혼합한 건조방식에서 전도성 금속 잉크의 건조 및 큐어링 공정 특성에 관한 실험적 연구)

  • Kim, Young-Mo;Hong, Seung-Chan;Lee, Jai-Hyo
    • Journal of the Semiconductor & Display Technology
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    • v.9 no.2
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    • pp.73-78
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    • 2010
  • This research is about the drying and curing characteristic of conductivity metallic ink on-line curing device in order to improve the curing time for productivity in RFID Gravure printing. The curing process is carried out to increase the electric conductivity after the metallic ink is printed on the substrate. The metal ink is composed of nano-sized silver or copper particles. In this research, the combined IR and Hot air curing system is used and its results is compared with those of oven, IR and Hot Air type respectively. Generally the curing time in the past is about 3 minutes. But the combined system (IR+Hot Air) in this research shows that curing time is less than 30 seconds. These results is much faster than those of other system. This study can be help to make Roll-to-Roll drying and curing process for mass and continuous production on-line.

Surface Preparation of III-V Semiconductors

  • Im, Sang-U
    • Proceedings of the Korean Vacuum Society Conference
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    • 2015.08a
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    • pp.86.1-86.1
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    • 2015
  • As the feature size of Si-based semiconductor shrinks to nanometer scale, we are facing to the problems such as short channel effect and leakage current. One of the solutions to cope with those issues is to bring III-V compound semiconductors to the semiconductor structures, because III-V compound semiconductors have much higher carrier mobility than Si. However, introduction of III-V semiconductors to the current Si-based manufacturing process requires great challenge in the development of process integration, since they exhibit totally different physical and chemical properties from Si. For example, epitaxial growth, surface preparation and wet etching of III-V semiconductors have to be optimized for production. In addition, oxidation mechanisms of III-V semiconductors should be elucidated and re-growth of native oxide should be controlled. In this study, surface preparation methods of various III-V compound semiconductors such as GaAs, InAs, and GaSb are introduced in terms of i) how their surfaces are modified after different chemical treatments, ii) how they will be re-oxidized after chemical treatments, and iii) is there any effect of surface orientation on the surface preparation and re-growth of oxide. Surface termination and behaviors on those semiconductors were observed by MIR-FTIR, XPS, ellipsometer, and contact angle measurements. In addition, photoresist stripping process on III-V semiconductor is also studied, because there is a chance that a conventional photoresist stripping process can attack III-V semiconductor surfaces. Based on the Hansen theory various organic solvents such as 1-methyl-2-pyrrolydone, dimethyl sulfoxide, benzyl alcohol, and propylene carbonate, were selected to remove photoresists with and without ion implantation. Although SPM and DIO3 caused etching and/or surface roughening of III-V semiconductor surface, organic solvents could remove I-line photoresist without attack of III-V semiconductor surface. The behavior of photoresist removal depends on the solvent temperature and ion implantation dose.

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Facilitation of the four-mask process by the double-layered Ti/Si barrier metal for oxide semiconductor TFTs

  • Hino, Aya;Maeda, Takeaki;Morita, Shinya;Kugimiya, Toshihiro
    • Journal of Information Display
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    • v.13 no.2
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    • pp.61-66
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    • 2012
  • The double-layered Ti/Si barrier metal is demonstrated for the source/drain Cu interconnections in oxide semiconductor thin-film transistors (TFTs). The transmission electromicroscopy and ion mass spectroscopy analyses revealed that the double-layered barrier structure suppresses the interfacial reaction and the interdiffusion at the interface after thermal annealing at $350^{\circ}C$. The underlying Si layer was found to be very useful for the etch stopper during wet etching for the Cu/Ti layers. The oxide TFTs with a double-layered Ti/Si barrier metal possess excellent TFT characteristics. It is concluded that the present barrier structure facilitates the back-channel-etch-type TFT process in the mass production line, where the four- or five-mask process is used.

Design and Analysis of a Clean Non-contact type Conveyor's Driving Mechanism for Vertical Transfer of FPD Glass (대면적 FPD 글래스 수직 이송용 클린 비접촉식 컨베이어 구동부 설계 및 해석)

  • Shim, Jae-Hong
    • Journal of the Semiconductor & Display Technology
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    • v.8 no.4
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    • pp.71-76
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    • 2009
  • The clean non-contact type conveyor system for vertical transfer of large size FPD(Flat Panel Display) glasses has been installed at FPD production line just since a few years ago. The most important part of the conveyor is the 3 axis permanent magnet rollers faced orthogonally in pairs. However, the systematic design method about it has not been proposed yet. In this paper, we studied a design analysis for determining geometrical parameters of the magnetic roller by using a commercial FEM tool of the 3D Maxwell. Through a series of simulation, we obtained the relationship of several geometrical parameters affecting the torque of the conveyor.

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Efficient Auto Measure Sampling Method for Semiconductor Line (반도체 라인의 효율적 계측을 위한 자동 계측 샘플링 방식에 관한 연구)

  • Kim, Tae-Yeob;Sun, Dong-Seok;Lee, Jee-Hyung
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.58 no.12
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    • pp.2505-2510
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    • 2009
  • Semiconductor processes need measurement to confirm where there are problems in quality after progresses manufacturing process. This paper suggests equipment and automatic measure sampling method that control monitoring ratio according to change point occurrence availability of process that is not measure method by the existent simple ratio rate. This paper defines measure section as ailment section, metastable section and stability section by change point standard and create statistical model of each section and developed suitable measure rate model by section. As a result, we have accomplished maximum throughput and minimum sampling number that needs to maintain constant level of quality. Proposed method minimizes load of measure process by brings production quality sophistication and decrease of process badness and lowers measure rate in stable section making perception about problem occurrence quick heightening measure rate at change point occurrence.

Matching Improvement of RF Matcher for Plasma Etcher (식각장비의 RF 정합모듈 성능 개선)

  • Sul, Yong-Tae;Lee, Eui-Yong;Kwon, Hyuk-Min
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.9 no.2
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    • pp.327-332
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    • 2008
  • New RF matcher module has been proposed in this paper for improvement of RF matcher in plasma etcher system using in semiconductor and display panel manufacturing process. New designed warm gear was used instead of bevel gear in new driving module, and control system was re-arranged with one-chip micro-process technique. The matching performance of new match module was improved in various process condition with reduction of backlash and matching time, and flexible motion of motor compared commercial match module. However this new type RF match module will improve the productivity in etching process of the mass production line.

Development of the Chemical Flow Control System for Spinner Equipment in Semiconductor Manufacturing Process (반도체 제조공정의 스피너 장비를 위한 약액 흐름제어 시스템 개발)

  • Park, Hyoung-Keun
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.12 no.4
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    • pp.1812-1816
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    • 2011
  • This research developed chemical flow control system(CFCS) essential for spinner equipment in nano semiconductor manufacturing process under the 100nm to prevent complex process defect due to missing spread after chemical injection. The devices developed in this research, which can be swiftly replaced in case abnormal state element changes or wafer manufacturing defect occurs, are anticipated to improve module yield as well as real-time monitoring on the state element. In addition, as a result of mounting H/W and S/W system to control detailed operation sequence in production line and executing performance check and verification, we can be exactly detected in five abnomal process type.

BUMPLESS FLIP CHIP PACKAGE FOR COST/PERFORMANCE DRIVEN DEVICES

  • Lin, Charles W.C.;Chiang, Sam C.L.;Yang, T.K.Andrew
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2002.09a
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    • pp.219-225
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    • 2002
  • This paper presents a novel "bumpless flip chip package"for cost! performance driven devices. Using the conventional electroplating and etching processes, this package enables the production of fine pitch BGA up to 256 I/O with single layer routing. An array of circuitry down to $25-50{\mu}{\textrm}{m}$ line/space is fabricated to fan-in and fan-out of the bond pads without using bumps or substrate. Various types of joint methods can be applied to connect the fine trace and the bond pad directly. The resin-filled terminal provides excellent compliancy between package and the assembled board. More interestingly, the thin film routing is similar to wafer level packaging whereas the fan-out feature enables high lead count devices to be accommodated in the BGA format. Details of the design concepts and processing technology for this novel package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with die-level and system-level design teams is highlighted as critical to an optimal design for performance and cost.

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Improvement of Vibration Performance for Wafer Transfer Robot using Frequency Analysis of Motion Profile (모션프로파일의 주파수분석을 통한 웨이퍼 이송로봇의 진동성능 향상)

  • Shin, Dongwon;Yun, Jang Kyu
    • Journal of the Korean Society for Precision Engineering
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    • v.31 no.8
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    • pp.697-703
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    • 2014
  • This paper is study of solving vibration problem occurred in moving hand of wafer transfer robot in semiconductor manufacturing line. Long settling time for decreasing vibration makes low production rate, and moreover the excessive vibration of hand sometimes breaks the wafer in a cassette. The ways of reducing the moving speed and changing the type of motion profile did not help for lessening vibration. Therefore, we analyzed the mechanical property of the hand such as natural frequency, and frequency component of the motion profile currently used in the manufacturing line. In several conditions of motion profile, we found the best condition of which the frequency component in near of natural frequency of the hand is minimal and this induced small vibration in moving hand. The results were verified theoretically and experimentally using frequency analysis.