• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.12
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• pp.5832-5837
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• 2011

In this paper, we designed a thermal shutdown block for LED applications using a 1 ${\mu}m$ CMOS process. The proposed thermal shutdown protection circuit has been designed with a shut-off temperature of $120^{\circ}C$ and a restart temperature of $90^{\circ}C$ which are suitable conditions for LED driver IC. Also, we got SPICE simulation results of the circuit about process variation of the semiconductor fabrication. From simulation data, process variation rate of the proposed circuit are within 7 % which are good results compared with conventional BJT current mirror type circuit. Finally, we confirmed that the thermal shutdown circuit has good thermal protection function within a LED driver IC.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.404-416
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• 2015

Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.9
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• pp.701-709
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• 2011

In semiconductor wafer fabrication, etching is one of the most critical processes, by which a material layer is selectively removed. Because of difficulty to correct a mistake caused by over etching, it is critical that etch should be performed correctly. This paper proposes a new approach for etch endpoint detection of small open area wafers. The traditional endpoint detection technique uses a few manually selected wavelengths, which are adequate for large open areas. As the integrated circuit devices continue to shrink in geometry and increase in device density, detecting the endpoint for small open areas presents a serious challenge to process engineers. In this work, a high-resolution optical emission spectroscopy (OES) sensor is used to provide the necessary sensitivity for detecting subtle endpoint signal. Partial Least Squares (PLS) method is used to analyze the OES data which reduces dimension of the data and increases gap between classes. Support Vector Machine (SVM) is employed to detect endpoint using the data after PLS. SVM classifies normal etching state and after endpoint state. Two data sets from OES are used in training PLS and SVM. The other data sets are used to test the performance of the model. The results show that the trained PLS and SVM hybrid algorithm model detects endpoint accurately.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.523-523
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• 2012

As the wafer geometric requirements continuously complicated and minutes in tens of nanometers, the expectation of real-time add-on sensors for in-situ plasma process monitoring is rapidly increasing. Various industry applications, utilizing plasma impedance monitor (PIM) and optical emission spectroscopy (OES), on etch end point detection, etch chemistry investigation, health monitoring, fault detection and classification, and advanced process control are good examples. However, process monitoring in semiconductor manufacturing industry requires non-invasiveness. The hypothesis behind the optical monitoring of plasma induced ion current is for the monitoring of plasma induced charging damage in non-invasive optical way. In plasma dielectric via etching, the bombardment of reactive ions on exposed conductor patterns may induce electrical current. Induced electrical charge can further flow down to device level, and accumulated charges in the consecutive plasma processes during back-end metallization can create plasma induced charging damage to shift the threshold voltage of device. As a preliminary research for the hypothesis, we performed two phases experiment to measure the plasma induced current in etch environmental condition. We fabricated electrical test circuits to convert induced current to flickering frequency of LED output, and the flickering frequency was measured by high speed optical plasma monitoring system (OPMS) in 10 kHz. Current-frequency calibration was done in offline by applying stepwise current increase while LED flickering was measured. Once the performance of the test circuits was evaluated, a metal pad for collecting ion bombardment during plasma etch condition was placed inside etch chamber, and the LED output frequency was measured in real-time. It was successful to acquire high speed optical emission data acquisition in 10 kHz. Offline measurement with the test circuitry was satisfactory, and we are continuously investigating the potential of real-time in-situ plasma induce current measurement via OPMS.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.4
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• pp.556-561
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• 2022

In this paper, we present a block media communication (BMC) system which employs powerline communication to the equipments used in the welding process for ship-assembly and uses metal block as a communication medium. Inductive couplers are installed on digital feeder and pin jig. Information signal is added to the current generated by the welding gun, and applied to the block. When the welding operation starts, information generated in the field is transmitted to the monitoring server in real-time. The field test on the BMC system confirms that the transmitted data are correctly received at the server. Since the proposed system can be built without any changes to the existing welding process, it is helpful to increase competitiveness of the shipbuilding industry through smart factory of shipyards. It is also possible to quickly respond to emergency situations that may occur to workers in an electromagnetic wave shielding environment or a closed space, the effect of preventing industrial accidents will be great.

• The KIPS Transactions:PartD
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• v.11D no.3
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• pp.709-716
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• 2004

This paper describes an intelligent real-time monitoring system of a semiconductor processing equipment, which determines normal or not for a wafer in processing, using multiple time-series pattern recognition. The proposed system consists of three phases, initialization, learning and real-time prediction. The initialization phase sets the weights and tile effective steps for all parameters of a monitoring equipment. The learning phase clusters time series patterns, which are producted and fathered for processing wafers by the equipment, using LBG algorithm. Each pattern has an ACI which is measured by a tester at the end of a process The real-time prediction phase corresponds a time series entered by real-time with the clustered patterns using Dynamic Time Warping, and finds the best matched pattern. Then it calculates a predicted ACI from a combination of the ACI, the difference and the weights. Finally it determines Spec in or out for the wafer. The proposed system is tested on the data acquired from etching device. The results show that the error between the estimated ACI and the actual measurement ACI is remarkably reduced according to the number of learning increases.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.168-174
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• 2012

This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed symbol as well as the current symbol is sent for easing the sensing operation at receiver end. With this approach, the voltage swing on the channel for reliable sensing can be reduced, resulting in performance improvement in terms of power consumption, peak current, and delay spread due to PVT variations, as compared to the conventional repeater insertion schemes. Evaluation for on-chip interconnects having various lengths in a 130 nm CMOS process indicated that the proposed on-chip interconnect scheme achieved a power reduction of up to 71.3%. The peak current during data transmission and the delay spread due to PVT variations were also reduced by as much as 52.1% and 65.3%, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.212-218
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• 2012

A stereo vision is able to build three-dimensional maps of its environment. It can provide much more complete information than a 2D image based vision but has to process, at least, that much more data. In the past decade, real-time stereo has become a reality. Some solutions are based on reconfigurable hardware and others rely on specialized hardware. However, they are designed for their own specific applications and are difficult to extend their functionalities. This paper describes a vision system based on a System on a Chip (SoC) platform. A real-time stereo image correlator is implemented using Sum of Absolute Difference (SAD) algorithm and is integrated into the vision system using AMBA bus protocol. Since the system is designed on a pre-verified platform it can be easily extended in its functionality increasing design productivity. Simulation results show that the vision system is suitable for various real-time applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.316-324
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• 2010

In this paper, we design a 256 kbits EEPROM for a MCU (Microcontroller unit) with the wide voltage range of 1.8 V to 5.5 V. The memory space of the EEPROM is separated into a program and data region. An option memory region is added for storing user IDs, serial numbers and so forth. By making HPWs (High-voltage P-wells) of EEPROM cell arrays with the same bias voltages in accordance with the operation modes shared in a double word unit, we can reduce the HPW-to-HPW space by a half and hence the area of the EEPROM cell arrays by 9.1 percent. Also, we propose a page buffer circuit reducing a test time, and a write-verify-read mode securing a reliability of the EEPROM. Furthermore, we propose a DC-DC converter that can be applied to a MCU with the wide voltage range. Finally, we come up with a method of obtaining the oscillation period of a charge pump. The layout size of the designed 256 kbits EEPROM IP with MagnaChip's 0.18 ${\mu}m$ EEPROM process is $1581.55{\mu}m{\times}792.00{\mu}m$.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.71-78
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• 2012

This paper describes trends in conventional scaling compared with advanced technologies such as 3D integration (3DI) and bumpless through-silicon via (TSV) processes, as well as the characteristics of CMOS (Complementary Metal Oxide Semiconductor) Logic device after thinning the wafers to less than $10{\mu}m$. Each module process including thinning, stacking, and TSV, is optimized for 3D Wafer-on-Wafer (WOW) application. Optimization results are discussed with valuable data in detail. Since vertical wiring of bumpless TSV can be connected directly to the upper and lower substrates by self-alignment, bumps are not necessary when TSV interconnects are used.