• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2004.05a
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• pp.123-128
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• 2004

Semiconductor Wet Station has a very important place in semiconductor process. It is important that to discharge chemical with fit concentration and temperature using chemical supply system for clean process. The chemical supply system which is used currently is not only difficult to make a fit mixing rate of chemical which is need in clean process, but also difficult to make fit concentration and temperature. Moreover, it has high stability but it is inefficient spatially because its volume is great. We propose In-line System to improve system with implement analysis of fluid and thermal transfer on chemical supply system and understand problem of system.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.153.2-153
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• 1998

• Journal of Korean Society of Occupational and Environmental Hygiene
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• v.22 no.1
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• pp.52-59
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• 2012

Objectives: The purpose of this study was to evaluate the exposure possibility of by-products during the semiconductor manufacturing processes. Methods: The authors investigated types of chemicals generated during semiconductor manufacturing processes by the qualitative experiment on generation of by-products at the laboratory and a literature survey. Results: By-products due to decomposition of photoresist by UV-light during the photo-lithography process, ionization of arsine during the ion implant process, and inter-reactions of chemicals used at diffusion and deposition processes can be generated in wafer fabrication line. Volatile organic compounds (VOCs) such as benzene and formaldehyde can be generated during the mold process due to decomposition of epoxy molding compound and mold cleaner in semiconductor chip assembly line. Conclusions: Various types of by-products can be generated during the semiconductor manufacturing processes. Therefore, by-products carcinogen such as benzene, formaldehyde, and arsenic as well as chemical substances used during the semiconductor manufacturing processes should be controlled carefully.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.11
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• pp.98-105
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• 1999

As the IC(Integrated Circuit) has been densified and complicated, it is required to thorough process control to improve yield. Experts, for this purpose, focused on the process analysis automation, which is came from the strict data management in semiconductor manufacturing. In this paper, we presents the process analysis system that can analyze causes, for a output after processes. Also, the plasma etching process that highly affects yield among semiconductor process is modeled to predict a output before the process. To approach this problem, we use adaptively trained neural networks that exhibit superior accuracy over statistical techniques. And in comparison with methods in other paper, a method that history of trend for input data is considered is shown to offer advantage in both learning and prediction capability. This research regards CD(Critical Dimension) that is considerable in high integrated circuit as output variable of the prediction model.

• Journal of the Semiconductor & Display Technology
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• v.2 no.4
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• pp.13-17
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• 2003

An adaptor is designed for chamber impedance measurement of plasma process. Copper rod, fixed board and compensation circuit are the major components of the adaptor. An adaptor can be to measure chamber impedance on time unless stopping a process and Data to measure can do the database. We can use it to a criteria data for a failure diagnosis. So developed adaptor could be used for diagnosis the plasma process chamber in semiconductor industry.

• Journal of IKEEE
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• v.13 no.1
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• pp.65-70
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• 2009

We propose an ultrashort pulse optical code-division multiple-access (O-CDMA) scheme based on a pseudorandom binary M-sequence spectral phase encoding and decoding of coherent mode-locked laser pulses and perform a numerical simulation to analyze its feasibility. We demonstrate the ability to properly decode any of the multiple (eight) 10 Gbit/s users by the matched code selection of the spectral phase decoder. The peak power signal to noise ratio of properly and improperly decoded $8{\times}10 Gb/s$ signals could be greater than 15 for 127 M-sequence coding.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.1-7
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• 2020

The backside metallization process is typically used to attach a chip to a lead frame for semiconductor packaging because it has excellent bond-line and good electrical and thermal conduction. In particular, the backside metal with the Ag/Sn/Ag sandwich structure has a low-temperature bonding process and high remelting temperature because the interfacial structure composed of intermetallic compounds with higher melting temperatures than pure metal layers after die attach process. Here, we introduce a die attach process with the Ag/Sn/Ag sandwich structure to apply commercial semiconductor packages. After the die attachment, we investigated the evolution of the interfacial structures and evaluated the shear strength of the Ag/Sn/Ag sandwich structure and compared to those of a commercial backside metal (Au-12Ge).

• Journal of the Korea Society for Simulation
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• v.14 no.4
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• pp.55-68
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• 2005

The advancement in semiconductor technology is leading toward smaller critical dimension designs and larger wafer manufactures. Due to such phenomena, semiconductor industry is in need of an accurate control of the process. Photolithography is one of the key processes where the pattern of each layer is formed. In this process, precise superposition of the current layer to the previous layer is critical. Therefore overlay parameters of the semiconductor photolithography process is targeted for this research. The complex relationship among the input parameters and the output metrologies is difficult to understand and harder yet to model. Because of the superiority in modeling multi-nonlinear relationships, neural networks is used for the simulator modeling. For training the neural networks, conjugate gradient method is employed. An experiment is performed to evaluate the performance among the proposed neural network simulator, stepwise regression model, and the currently practiced prediction model from the test site.

• International Journal of Precision Engineering and Manufacturing
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• v.5 no.3
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• pp.11-18
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• 2004

In this paper, the classification of artificial defects in semiconductor packages is studied by using pattern recognition technology. For this purpose, the pattern recognition algorithm includes the user made MATLAB code. And preprocess is made of the image process and self-organizing map, which is the input of the back-propagation neural network and the dimensionality reduction method, The image process steps are data acquisition, equalization, binary and edge detection. Image process and self-organizing map are compared to the preprocess method. Also the pattern recognition technology is applied to classify two kinds of defects in semiconductor packages: cracks and delaminations.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.429-432
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• 1987

A new LOCOS (Local Oxidation of Silicon) process using a thin nitride film directly deposited on the silicon substrate by LPCVD has been developed in order to reduce the bird's beak length. SEM studies showed that nitride thickness of 50nm can decrease the bird's beak length down to 0.2um with 450nm field oxide. No crystalline defects are observed around the bird's beak after the Wright etch. A 30% improvement in current density was obtained when this new method was applied to MOS transistors (W/L*2.9/20.4) compared to conventional LOCOS process (bird's beak length=0.7um). Other various electrical parameters improved by this new simple LOCOS process are reported in this paper.