• 반도체디스플레이기술학회지
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• 제3권3호
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• pp.5-9
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• 2004

A new wafer level packaging scheme is presented as an alternative to MEMS package. The proof-of-concept structure is fabricated and evaluated to confirm the feasibility of the idea for MEMS wafer level packaging. The scheme of this work is developed using an electroplated tin (Sn) solder. The critical difference over conventional ones is that wafers are laterally bonded by solder reflow after LEGO-like assembly. This lateral bonding scheme has merits basically in morphological insensitivity and its better bonding strength over conventional ones and also enables not only the hermetic sealing but also its electrical interconnection solving an open-circuit problem by notching through via-hole. The bonding strength of the lateral bonding is over 30 Mpa as evaluated under shear and the hermeticity of the encapsulation is 2.0$\times10^{-9}$mbar.$l$/sec as examined by pressurized Helium leak rate. Results show that the new scheme is feasible and could be an alternative method for high yield wafer level packaging.

• 마이크로전자및패키징학회지
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• 제23권1호
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• pp.1-10
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• 2016

Nowadays, the importance of role of the international standardization keeps increasing substantially. We have already known that international standards have a huge impact on many companies, industries and nations. So far, it has been thought that standardizations are needed after the new products come into the market and are mass-produced in order to encourage the use of the products, systems and services. Standardization will make the products more safe, efficient, and environmentally friendly for the users. However, in these days, a paradigm of the standardization has been changed. International standard becomes a tool for dominating global market and is the most important ingredients of the competitiveness and economic progress of the nation and enterprises. Many countries like Japan, Germany and U.S. use the standardization as an effective method to dominate the market and monopolized the new technologies. Therefore, worldwide competition for the standardization of the new technology become fierce. Korea is leading the technology in semiconductor field. However, activities of international standardization are not sufficient. In order to boost the standardization activities in Korea from industry, academia, and research institute, this paper briefly introduce the international standard organization and some critical issues for next-generation semiconductor memory such as flexible semiconductor, automobile semiconductor and wearable devices.

• 마이크로전자및패키징학회지
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• 제30권1호
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• pp.1-16
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• 2023

전기차용 전력변환모듈의 성능향상 요구와 종래의 Si 전력반도체의 한계 극복을 위해 차세대 전력반도체인 wide-bandgap (WBG) 기반 전력반도체로의 전환이 가속화되고 있다. WBG 전력반도체로의 전환을 위해 전력변환모듈 패키징 소재 역시 높은 고온 내구성을 요구받고 있다. 전력변환모듈 패키징 공정 중 하나인 Ag 소결 다이접합 기술은 종래의 고온용 Pb 솔더링의 대체 기술로 주목받고 있다. 본 논문에서는 Ag 소결 다이접합 기술 관련 최신 연구동향에 대해 소개하고자 한다. 소결 다이접합 공정 조건에 따른 접합부 특성을 비교하고 Ag 소결층의 3차원 이미지 구현에 따른 다공성 Ag 소결 접합부의 물성 측정 방법론에 대해 고찰하였다. 또한 열충격 및 파워사이클 신뢰성 평가 연구동향을 분석하였다.

• 마이크로전자및패키징학회지
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• 제24권1호
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• pp.17-25
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• 2017

Recently, research and application for a power module have been actively studied according to the increasing demand for the production of vehicles, smartphones and semiconductor devices. The power modules based on the transient liquid phase (TLP) technology for bonding of power semiconductor devices have been introduced in this paper. The TLP bonding has been widely used in semiconductor packaging industry due to inhibiting conventional Pb-base solder by the regulation of end of life vehicle (ELV) and restriction of hazardous substances (RoHS). In TLP bonding, the melting temperature of a joint layer becomes higher than bonding temperature and it is cost-effective technology than conventional Ag sintering process. In this paper, a variety of TLP bonding technologies and their characteristics for bonding of power module have been described.

• 마이크로전자및패키징학회지
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• 제21권2호
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• pp.71-78
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• 2014

Silicon has been most widely used semiconductor material for power electronic systems. However, Si-based power devices have attained their working limits and there are a lot of efforts for alternative Si-based power devices for better performance. Advances in power electronics have improved the efficiency, size, weight and materials cost. New wide band gap materials such as SiC have now been introduced for high power applications. SiC power devices have been evolved from lab scale to a viable alternative to Si electronics in high-efficiency and high-power density applications. In this article, the potential impact of SiC devices for power applications will be discussed along with their Si counterpart in terms of higher switching performance, higher voltages and higher power density. The recent progress in the development of high voltage power semiconductor devices is reviewed. Future trends in device development and industrialization are also addressed.

• 한국산학기술학회논문지
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• 제3권4호
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• pp.290-294
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• 2002

본 논문은 반도체 패키징 제조에서 사용되고 있는 반도체 금형을 CAD/CAM을 활용하여 직접 제작하였다. 원래 반도체 금형은 강도와 열성이 아주 좋은 ASP23 재질을 사용하며 매우 고가이다. 또한 특수도금, 열처리와 정밀한 가공이 되어야 정상적인 반도체 패키징을 할 수 있다. 제작 과정은 CAD/CAM을 활용하여 직접 제작하였으므로 반도체 금형의 제작 방향을 제시하는 계기가 되었다.

• 한국정밀공학회지
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• 제32권9호
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• pp.799-805
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• 2015

The further development of information, communication and digital media technologies requires the use of advanced, miniaturized semiconductor chips that operate at a high frequency. Die bonding and wire bonding methods for semiconductor packaging have been replaced by direct attachment to the substrate after forming a bump on the chip. However, the height of the bump or ball is an important factor for defects during assembly. This paper proposes an algorithm to measure the height of the bumps or balls in semiconductor packaging with greater accuracy. The performance of the proposed algorithm is experimentally validated. Non-contact 3D measurements of a shiny round ball is quite difficult, and it is not easy to obtain accurate data. This paper thus proposes an optical method and technique to improve the measurement accuracy.

• 반도체디스플레이기술학회지
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• 제16권2호
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• pp.19-26
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• 2017

The cure properties of ethoxysilyl bisphenol A type epoxy resin (Ethoxysilyl-DGEBA) systems with different hardeners were investigated, comparing with DGEBA and Diallyl-DGEBA epoxy resin systems. The cure kinetics of these systems were analyzed by differential scanning calorimetry with an isothermal approach, and the kinetic parameters of all systems were reported in generalized kinetic equations with diffusion effects. The Ethoxysilyl-DGEBA epoxy resin system showed lower cure conversion rates than DGEBA and Diallyl-DGEBA epoxy resin systems. The conversion rates of these epoxy resin systems with DDM hardener are lower than those with HF-1M hardener. It can be considered that the optimum hardener for Ethoxysilyl-DGEBA epoxy resin system is Phenol Novolac type. These lower cure conversion rates in the Ethoxysilyl-DGEBA epoxy resin systems could be explained by the retardation of reaction molecule movements according to the formation of organic-inorganic hybrid network structure by epoxy and ethoxysilyl group in Ethoxysilyl- DGEBA epoxy resin system.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)

• 센서학회지
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• 제31권6호
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• pp.361-365
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• 2022

Advanced packaging demands are driven by the need for dense integration systems. Consequently, stacked packaging technology has been proposed instead of reducing the ultra-fine patterns to secure economic feasibility. This study proposed an effective packaging process technology for semiconductor devices using a 9-inch dicing die attach film (DDAF), wherein the die attach and dicing films were combined. The process involved three steps: tape lamination, dicing, and bonding. Following the grinding of a silicon wafer, the tape lamination process was conducted, and the DDAF was arranged. Subsequently, a silicon wafer attached to the DDAF was separated into dies employing a blade dicing process with a two-step cut. Thereafter, one separated die was bonded with the other die as a substrate at 130 ℃ for 2 s under a pressure of 2 kgf and the chip was hardened at 120 ℃ for 30 min under a pressure of 10 kPa to remove air bubbles within the DAF. Finally, a curing process was conducted at 175 ℃ for 2 h at atmospheric pressure. Upon completing the manufacturing processes, external inspections, cross-sectional analyses, and thermal stability evaluations were conducted to confirm the optimality of the proposed technology for application of the DDAF. In particular, the shear strength test was evaluated to obtain an average of 9,905 Pa from 17 samples. Consequently, a 3D integration packaging process using DDAF is expected to be utilized as an advanced packaging technology with high reliability.