• Journal of the Semiconductor & Display Technology
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• v.11 no.2
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• pp.63-69
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• 2012

As decreasing size of chips, the need of wafer level packaging is increased in semi-conductor and display industries. Temperature uniformity is a crucial factor in vacuum soldering process to guarantee quality of bonding between chips and wafer. In this paper, a stepwise iterative algorithm has been suggested to obtain output profile of each heat source. Since this algorithm is based on open-loop stepwise iterative experimental technique, it is easier to implement and cost effective than real time feedback controls. Along with some experiments, it was shown that the suggested algorithm can remarkably improve temperature uniformity of wafer during whole heating process compared with the ordinary manual trial-and error method.

• Journal of the Korean Society for Precision Engineering
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• v.30 no.7
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• pp.702-708
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• 2013

The white-light scanning interferometer (WSI) is an effective optical measurement system for high-precision industries (e.g., flat-panel display and electronics packaging manufacturers) and semiconductor manufacturing industries. Its major disadvantages include a slow image-capturing speed for interferogram acquisition and a high computational cost for peak-detection on the acquired interferogram. Here, a WSI system is proposed for the semiconductor inspection process. The new imaging acquisition technique uses an 'on-the-fly' imaging system. During the vertical scanning motion of the WSI, interference fringe images are sequentially acquired at a series of pre-defined lens positions, without conventional stepwise motions. To reduce the calculation time, a parallel computing method is used to link multiple personal computers (PCs). Experiments were performed to evaluate the proposed high-speed WSI system.

• Journal of the Semiconductor & Display Technology
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• v.19 no.1
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• pp.29-35
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• 2020

The cure characteristics of three kinds of naphthalene type epoxy resins(NET-OH, NET-MA, NET-Epoxy) with a 2-methyl imidazole(2MI) catalyst were investigated for preparing sheet epoxy molding compound(SEMC) for wafer level package(WLP) applications, comparing with diglycidyl ether of bisphenol-A(DGEBA) and 1,6-naphthalenediol diglycidyl ether(NE-16) epoxy resin. The cure kinetics of these systems were analyzed by differential scanning calorimetry with an isothermal approach, and the kinetic parameters of all systems were reported in generalized kinetic equations with diffusion effects. The NET-OH epoxy resin represented an n-th order cure mechanism as like NE-16 and DGEBA epoxy resins, however, the NET-MA and NET-Epoxy resins showed an autocatalytic cure mechanism. The NET-OH and NET-Epoxy resins showed higher cure conversion rates than DGEBA and NE-16 epoxy resins, however, the lowest cure conversion rates can be seen in the NET-MA epoxy resin. Although the NETEpoxy and NET-MA epoxy resins represented higher cure reaction conversions comparing with DGEBA and NE-16 resins, the NET-OH showed the lowest cure reaction conversions. It can be figured out by kinetic parameter analysis that the lowest cure conversion rates of the NET-MA epoxy resin are caused by lower collision frequency factor, and the lowest cure reaction conversions of the NET-OH are due to the earlier network structures formation according to lowest critical cure conversion.

• Journal of the Korea Society for Simulation
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• v.20 no.3
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• pp.49-58
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• 2011

The workloads of facilities and laborers are important for the capacity planning in a factory. They are always referenced whenever a factory develops a new product, increases the production quantity and makes a plan of new investment. There are many measuring methods for estimating the workload effectiveness of facilities and laborers. In this paper, various measuring methods including survey, work sampling, micro-motion study, data gathering from ERP system and simulation, are analyzed for comparing the accuracy of workload. This case study is conducted in a Korean company that produces semiconductor parts like leadframe and packaging substrate.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.10a
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• pp.293-316
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• 2006

[ $\blacksquare$ ] I/O Signal $\square$ We see adequate margin for the RC B design $\square$ Minimum ODW value is 328ps using Ac to DC measurement for the read case. $\square$ Minimum ODW value is 350ps using AC to DC mesurement method for the write case. $\blacksquare$ CLK Signal $\square$ The slew-rate decreases when the Cterm value increases $\square$ Lower slew-rate could effect delay and jitter. $\square$ There are some ldge issues during transitions with lower Cterm and without Cterm. $\square$ Our recommendation for the Cterm value range is between 1.5pF to 2.4pF. $\blacksquare$ ADD/CMD/Ctrl Signal $\square$ High output slew-rate at low VDD causes ring back that reduces voltage margin because of x-talk. $\square$ 30ohm Rterm for the CTRL signal shows a better signal integrity result compared to 36ohm.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.09a
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• pp.79-94
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• 2002

Root cause -Thermal expansion coefficient mismatch -Tape warpage -Initial die crack (die roughness) Guideline for failure prevention -Optimized tape/Substrate design for minimizing the warpage -Fine surface of die backside Root cause -Thermal expansion coefficient mismatch - Repetitive bending of a signal trace during TC cycle - Solder mask damage Guideline for failure prevention - Increase of trace width - Don't make signal trace passing the die edge - Proper material selection with thick substrate core Root cause -Thermal expansion coefficient mismatch -Creep deformation of solder joint(shear/normal) -Material degradation Guideline for failure Prevention -Increase of solder ball size -Proper selection of the PCB/Substrate thickness -Optimal design of the ball array -Solder mask opening type : NSMD -In some case, LGA type is better

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.83-88
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• 2003

The optoelectronic characteristics of semiconducto-atomic superlattice as a function of deposition temperature and annealing conditions have been studied. The nanocrystalline silicon/adsorbed oxygen superlattice formed by molecular beam epitaxy(MBE) system. As an experimental result, the superlattice with multilayer Si-O structure showed a stable photoluminescence(PL) and good insulating behavior with high breakdown voltage. This is very useful promise for Si-based optoelectronics and quantum devices as well as for the replacement of silicon-on-insulator (SOI) in ultra-high speed and lower power CMOS devices in the future, and it can be directly integrated with silicon ULSI processing.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.251-255
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• 2003

탄화규소 반도체에 대한 오옴성 금속 접촉 성질을 조사하기 위해 3종류의 금속 (Ni, Co, Cu)을 세척한 탄화규소 반도체 위에 직접 증착하여 전기적 성질을 조사 비교하였다. 이들 금속에 대한 오옴성 성질은 금속종류 뿐만 아니라 열처리조건에 대해서도 크게 좌우됨을 알 수 있었다. 열처리는 급속열처리 장치를 이용한 진공상태 및 환원 분위기에서 2-step 방법으로 시행하였다. 접합비 저항은 TLM 구조를 만들었으며 면저항$(R_s)$, 접촉저항$(R_c)$, 이동거리$(L_T)$, 패드간거리(d), 저항$(R_T)$ 값을 구하면 접합비저항$(\rho_c)$ 값을 구하여 알려진 계산식에 의해 추정하였다. 가장 양호한 결과는 Cu 금속에 의한 접촉 결과이었으며 접합비저항$(\rho_c)$은 $1.2\times10^{-6}{\Omega}cm^2$의 낮은 값을 얻을 수 있었다. 열처리는 진공보다 환원분위기에서 수행한 시편이 양호한 전기적 성질을 가짐을 알 수 있었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.10-10
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• 2008

Flip chip technology is keeping pace with the increasing connection density of the ICs and is capable of transferring semiconductor performance to the printed circuit board. One of the most general flip chip technology is CPB technology presented by Intel. The CPTB technology has similar benefits with CPB but has simpler process and better reliability characteristics. In this paper, process sequence and structure of CPTB are presented.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.4
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• pp.31-34
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• 2002

For the mold die sticking mechanism, the major explanation is that the silica as a filler in EMC (epoxy molding compound) wears die surface to be roughened, which results in increase of adhesion strength. As the sticking behavior, however, showed strong dependency on the EMC models based on the experimental results from different semiconductor manufacturers, chemisorption or acid-base interaction is apt to be also functioning as major mechanisms. In this investigation, the plasma source ion implantation (PSII) using $O_2, N_2$, and $CF_4$ modifies sample surface to form a new dense layer and improve surface hardness, and change metal surface condition from hydrophilic to hydrophobic or vice versa. Through surface energy quantification by measuring contact angle and surface ion coupling state analysis by Auger, major governing mechanism for sticking issue was figured out to be a complex of mechanical and chemical factors.