• Design & Manufacturing
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• v.12 no.1
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• pp.47-51
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• 2018

As the IT industry rapidly progresses, the functions of electronic devices and display devices are integrated with high density, and the model is changed in a short period of time. To implement the integration technology, a uniform micro-pattern implementation technique to drive and control the product is required. The most important technology for the micro pattern generation is the exposure processing technology. Failure to implement the basic pattern in this process cannot satisfy the demands in the manufacturing field. In addition, the conventional exposure method of the mask method cannot cope with the small-scale production of various types of products, and it is not possible to implement a micro-pattern, so an alternative technology must be secured. In this study, the technology to implement the required micro-pattern in semiconductor processing is presented through the photolithography process and plasma etching.

• Corrosion Science and Technology
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• v.8 no.4
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• pp.148-152
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• 2009

The failure of a Zn-plated carbon steel pipe that served as a fire sprinkler was investigated in terms of the pipe's corrosion products. The pipes leaked through holes formed beneath the tubercles. The formation of oxygen concentration cell involves colonization of metal surface by aerobic bacteria or other slime formers, and anodic reaction beneath tubercle is accelerated by the presence of SRB, leading to the formation of hole beneath tubercle.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.344-350
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• 2011

Higher integrated density in 3D ICs also brings the difficulties of routing, which can cause the routing failure or re-design from beginning. Hence, precise congestion estimation at the early physical design stage such as floorplan is beneficial to reduce the total design time cost. In this paper, an effective estimation method of routing congestion is proposed for 3D ICs at floorplan stage. This method uses synthesized virtual signal nets, power/ground network and clock network to achieve the estimation. During the synthesis, the TSV location is also under consideration. The experiments indicate that our proposed method had small difference with the estimation result got at the post-placement stage. Furthermore, the comparison of congestion maps obtained with our method and global router demonstrates that our estimation method is able to predict the congestion hot spots accurately.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.71-78
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• 2013

In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-on-chip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.

• Journal of Power Electronics
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• v.15 no.1
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• pp.96-105
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• 2015

In recent years, the multilevel converters have been given more attention due to their modularity, reliability, failure management and multi stepped output waveform with less total harmonic distortion. This paper presents a novel symmetric multilevel inverter topology with reduced switching components to generate a high quality stepped sinusoidal voltage waveform. The series and parallel combinations of switches in the proposed topology reduce the total number of conducting switches in each level of output voltages. In addition, a comparison between the proposed topology with another topology from the literature is presented. To verify the proposed topology, the computer based simulation model is developed using MATLAB/Simulink and experimentally with a prototype model results are then compared.

• 한국전자현미경학회:학술대회논문집
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• 2001.11a
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• pp.18-22
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• 2001

A technique to characterize specific site of materials using a combination of a dedicated focused ion beam system(FIB), and Intermediate-voltage scanning transmission electron microscope(STEM) or transmission electron microscope(TEM) equipped with a scanning electron microscope(SEM) unit has been developed. The FIB system is used for preparation of electron transparent thin samples, while STEM or TEM is used for localization of a specific site to be milled in the FIB system. An FIB-STEM(TEM) compatible sample holder has been developed to facilitate thin sample preparation with high positional accuracy Positional accuracy of $0.1{\mu}m$ or better can be achieved by the technique. In addition, an FIB micro-sampling technique has been developed to extract a small sample directly from a bulk sample in a FIB system These newly developed techniques were applied for the analysis of specific failure in Si devices and also for characterization of a specific precipitate In a metal sample.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.427-431
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• 2005

In this study, 6' GaAs wafer bonding system is designed and optimized to bond 6 inches device wafer and material wafer. Bonding process is performed in vacuum environment and resin is used to bond two wafers. Vacuum module and double heating mechanisms are adopted to minimize wafer warpage and void. Structure and heat transfer analysis, et al of the core modules review the designed mechanisms are very effective in performance improvement. As a result, high productivity (tack time cut-down) and stabilized process can be obtained by reducing breakage failure of wafer.

• Journal of Radiation Industry
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• v.18 no.1
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• pp.79-87
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• 2024

In a previous study, the suitability for use of inspection equipment was evaluated at temperatures outside the quality assurance range. The quality assurance operating temperature of the safeguards equipment is 0~+40℃, and previous studies have confirmed the performance of the safeguards equipment for temperatures ranging from -40~+70℃. The scintillator-based verification equipment showed a shift in the centroid channel and a change in the count rate in all temperature ranges, and the semiconductor-based safeguards equipment generated Leakage Current and equipment failure. In this study, a retrofit was performed applying a vacuum housing to the safeguards equipment (Inspector-2000-based inspection equipment), and performance evaluation was performed at a low temperature and snowy site, and it was confirmed that the same performance was observed as the measurement results at room temperature.

• Journal of Intelligence and Information Systems
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• v.9 no.1
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• pp.157-177
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• 2003

This paper presents a comprehensive and successful application of data mining methodologies to improve and predict wafer yield in a semiconductor wafer fabrication system. As the wafer fabrication process is getting more complex and the volume of technological data gathered continues to be vast, it is difficult to analyze the cause of yield deterioration effectively by means of statistical or heuristic approaches. To begin with this paper applies a clustering method to automatically identify AUF (Area Uniform Failure) phenomenon from data instead of naked eye that bad chips occurs in a specific area of wafer. Next, sequential pattern analysis and classification methods are applied to and out machines and parameters that are cause of low yield, respectively. Furthermore, radial bases function method is used to predict yield of wafers that are in process. Finally, this paper demonstrates an information system, Y2R-PLUS (Yield Rapid Ramp-up, Prediction, analysis & Up Support), that is developed in order to analyze and predict wafer yield in a korea semiconductor manufacturer.

• Journal of Powder Materials
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• v.13 no.5 s.58
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• pp.321-326
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• 2006

Electronic packaging involves interconnecting, powering, protecting, and cooling of semiconductor circuits fur the use in a variety of microelectronic applications. For microelectronic circuits, the main type of failure is thermal fatigue, owing to the different thermal expansion coefficients of semiconductor chips and packaging materials. Therefore, the search for matched coefficients of thermal expansion (CTE) of packaging materials in combination with a high thermal conductivity is the main task for developments of heat sink materials electronics, and good mechanical properties are also required. The aim of this work is to develop copper matrix composites reinforced with carbon nanofibers. The advantages of carbon nanofibers, especially the good thermal conductivity, are utlized to obtain a composite material having a thermal conductivity higher than 400 W/mK. The main challenge is to obtain a homogeneous dispersion of carbon nanofibers in copper. In this paper, a technology for obtaining a homogeneous mixture of copper and nanofibers will be presented and the microstructure and properties of consolidated samples will be discussed. In order to improve the bonding strength between copper and nanofibers, different alloying elements were added. The microstructure and the properties will be presented and the influence of interface modification will be discussed.