• Design & Manufacturing
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• v.16 no.1
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• pp.15-20
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• 2022

This paper is about elimination the situation in which gas sensor data becomes inaccurate due to temperature control when a semiconductor gas sensor is driven. Recently, interest in semiconductor gas sensors is high because semiconductor sensors can be driven with small and low power. Although semiconductor-type gas sensors have various advantages, there is a problem that they must operate at high temperatures. First temperature control was configured to adjust the temperature value of the heater mounted on the gas sensor. At that time, in controlling the heater temperature, gas sensor data are fluctuated despite supplying same gas concentration according to the temperature controlled. To resolve this problem, gas and temperature are extracted as a data. And then, a relation function is constructed between gas and temperature data. At this time, it is included low pass filter to get the stable data. In this paper, we can find optimal gain and parameters between gas and temperature data by using genetic algorithm.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.30-35
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• 2020

A microlens has been fabricated by various methods such as a thermal reflow, hot embossing, diamond milling, etc. However, these methods require a relatively complex process to control the microlens shape. In this work, we report on a simple and cost-effective method to fabricate a cylindrical microlens (CML), which can diffuse light widely. We have employed a slot-die head with the dual plate (a meniscus guide with a protruded μ-tip and a shim with a slit channel) for coating of a narrow stripe using poly(methyl methacrylate) (PMMA). We have shown that the higher the coating gap, the lower the maximum coating speed, which causes an increase in the stripe width and thickness. The coated PMMA stripe has the concave shape. To make it in the shape of a convex microlens, we have applied the thermal reflow method. When the stripe thickness is small, however, its effect is negligible. To increase the stripe thickness, we have increased the number of repeated coating. With this scheme, we have fabricated the CML with the width of 223 ㎛ and the thickness of 7.3 ㎛. Finally, we have demonstrated experimentally that the CML can diffuse light widely, a feature demanded for light extraction efficiency of organic light-emitting diodes (OLEDs) and suppression of moiré patterns in displays.

• Journal of the Semiconductor & Display Technology
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• v.20 no.2
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• pp.43-50
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• 2021

The properties of materials which are widely used in industry fields like automobile, shipbuilding, casting, and electronics are strongly needed to have higher surface hardness, lower surface roughness, and higher compressive residual stress. As mentioned above, for the purpose of satisfying three factors, a variety of researches with respect to surface improvement have been actively studied and applied to every industry. SKD61 which is mostly used for die casting process of cold chamber method must meet a countless number of problems which are thermal, mechanical and chemical from highly specific working environment at high temperature over 600℃. Above all, in case of plunger sleeves used for die casting process, thermal fatigue has a bad effect on the surface of an inlet where molten metal is repeatedly injected. On account of it, plunger sleeves cause manufacturers to deteriorate quality of products. Therefore, in this paper, to improve the surface of an inlet of plunger sleeve, multilayer PVD coating using Ti, Cr and Mo is suggested. Furthermore, The surface characteristics such as surface roughness(Rsa, Rsq), surface hardness(HRB, HRC) and residual stress using XRD(X-ray diffractometer) of coated samples and specimens are studied and discussed.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.739-742
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• 2005

In this paper, an efficient detection algorithm for the flicker, which is caused by mismatching between light frequency and exposure time at CMOS image sensor (CIS), is proposed. The flicker detection can be implemented by specific hardware or complex signal processing logic. However it is difficult to implement on single chip image sensor, which has pixel, CDS, ADC, and ISP on a die, because of limited die area. Thus for the flicker detection, the simple algorithm and high accuracy should be achieved on single chip image sensor,. To satisfy these purposes, the proposed algorithm organizes only simple operation, which calculates the subtraction of horizontal luminance mean between continuous two frames. This algorithm was verified with MATLAB and Xilinx FPGA, and it is implemented with Magnachip 0.18 standard cell library. As a result, the accuracy is 95% in average on FPGA emulation and the consumed gate count is about 7,500 gates (@40MHz) for implementation using Magnachip 0.18 process.

• Journal of the Semiconductor & Display Technology
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• v.6 no.1 s.18
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• pp.17-22
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• 2007

Recent new packages such as MCP(Multi-Chip Package), QDP(Quadratic Die Package) and DDP(Dual Die Package) have stack type configuration. This kind of multi-layer package is thicker than single layer package. So there is need for the low height looping technology in wirebonder to make these packages thinner. There is stiff zone above ball in wirebonder wire which is called HAZ(Heat Affect Zone). When making low height loop (below $80\;{\mu}m$) with traditional forward loop, stiff wire in HAZ(Heat Affected Zone) above ball is bended and weakened. So the traditional forward looping method cannot be applied to low height loop. SSB(stand-off stitch) wire bonding method was applied to many packages which require very low loops. The drawback of SSB method is making frequent errors at making ball, neck damage above ball on lead and the weakness of ball bonding on lead. The alternative looping method is BNL(ball neckless) looping technology which is already applied to some package(DDP, QDP). The advantage of this method is faster in bonding process and making little errors in wire bonding compared with SSB method. This paper presents the result of BNL looping technology applied in assembly house and several issues related to low loop height consistence and BNL zone weakness.

• Design & Manufacturing
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• v.11 no.2
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• pp.25-28
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• 2017

Semiconductor equipment manufacturers desire to enhance efficiency of Sub Fab to increase semiconductor productivity. For this reason, Sub Fab equipment manufacturers are developing Integrated System that combined modules with multiple facilities. Integrated System is required to apply Mount Leveler of Wedge Type in compliance with weight increase compared with existing single equipment and product shape change. This thesis analyzes main design variables of components of Wedge Mount Leveler and carries out structure analysis using ANSYS, finite element analysis program Analysis shows that main design variables of components of Wedge Mount Leveler has self-locking condition by friction force of Wedge and adjusting bolt. Each friction force hinges upon Wedge angle and Friction Coefficient of contact surface and upon the thread angle and Friction Coefficient of contact surface. Also, as a result of carrying out structure analysis of Wedge Mount Leveler, deflection and stress appears in different depending on the height of the level.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.09a
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• pp.79-94
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• 2002

Root cause -Thermal expansion coefficient mismatch -Tape warpage -Initial die crack (die roughness) Guideline for failure prevention -Optimized tape/Substrate design for minimizing the warpage -Fine surface of die backside Root cause -Thermal expansion coefficient mismatch - Repetitive bending of a signal trace during TC cycle - Solder mask damage Guideline for failure prevention - Increase of trace width - Don't make signal trace passing the die edge - Proper material selection with thick substrate core Root cause -Thermal expansion coefficient mismatch -Creep deformation of solder joint(shear/normal) -Material degradation Guideline for failure Prevention -Increase of solder ball size -Proper selection of the PCB/Substrate thickness -Optimal design of the ball array -Solder mask opening type : NSMD -In some case, LGA type is better

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2003.04a
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• pp.161-166
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• 2003

The micro-extruding die is a die for manufacturing of fine-wire by extruding process. The fine-wire made from the micro-extruding can be effectively applied to fields of semiconductor parts and medical parts etc. It is predicted that the demand of fine-wire in industry is more and more increasing. In this study $\phi50\mu m$ micro-drill which is coated with diamond is used for drilling of super micro-hole sizes. For the machining of taper parts of entrance and exit, drill having $\phi50\mu\textrm{mm}$ inclination angle $20^{\circ}$and angle $30^{\circ}$ is used. This is useful for anti tool-breakage and excessive too-wear in drilling process. After micro-drilling, the polishing process by diamond abrasive and polishing wood s carried out for increasing surface roughness.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.202-205
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• 2002

The micro-extruding die is a die for manufacturing of fine-wire by extruding process. The fine-wire made from the micro-extruding can be effectively applied to fields of semiconductor parts and medical parts etc. It is predicted that the demand of fine-wire in industry is more and more increasing. In this study $\Phi$ 50${\mu}{\textrm}{m}$ micro-drill which is coated with diamond is used for drilling of super micro-hole sues. For the machining of taper parts of entrance and exit, drill having $\Phi$ 9mm inclination angle 20$^{\circ}$ is used. This is useful for anti tool-breakage in drilling process. After micro-drilling, the polishing process by abrasive is carried out for increasing surface roughness.

• ETRI Journal
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• v.36 no.4
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• pp.635-642
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• 2014

Three-dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through-silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal-aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal-aware floorplanning with min-cut die partitioning for 3D ICs. The proposed min-cut die partition methodology minimizes the number of connections between partitions based on the min-cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal-aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run-time.