• 한국산업융합학회 논문집
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• 제15권1호
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• pp.37-42
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• 2012

Trends in semiconductor equipment industry are to reduce the cost of producing semiconductor, semiconductor process development, facility development, and the minimum investment in terms of cost and quality. Semiconductor equipments are being considered to review and development is proceeding at the same time. In the first part of the semiconductor assembly process, in which the importance of die bonding process is emerging, a wide leadframe type die bonding machine is demanded for productivity. Die bonding machine was designed through experiments and by trial and error. It costs a lot of time and financial burden. The purpose of this study is to solve these problems by using the CAE tool 3G. By using finite element method, thermal analysis of die bonding machine to the various widths leadframe die bonder machine rail is performed for design.

• International Journal of Precision Engineering and Manufacturing
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• 제2권2호
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• pp.38-47
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• 2001

This paper decribes the development of computer-aided design of a very precise progressice die for lead frame of semiconductor chip. The approach to the system is based on knowledgr-based rules. Knowledge of fie이 experts. This system has been written in AutoLISP using AutoCAD ona personal computer and the I-DEAS drafting programming Language on the I-DEAS mater series drafting with on HP9000/715(64) workstation. Data exchange between AutoCAD and I-DEAS master series drafting is accomplished using DXF(drawing exchange format) and IGES(initial graphics exchange specification) files. This system is composed of six main modules, which are input and shape treatment, production feasibility check, strip layout, data conversion, die layout, and post processing modules. Based on Knowledge-based rules, the system considers several factors, such as V-notches, dimple, pad chamfer, spank, cavity punch, camber, coined area, cross bow, material and thickness of product, complexities of blank geometry and punch profiles, specifications of available presses, and the availability of standard parts. As forming processes and the die design system using 2D geometry recognition are integrated with the technology of process planning, die design, and CAE analysis, the standardization of die part for lead frames requiting a high precision process is possible. The die layout drawing generated by the die layout module s displayed in graphic form. The developed system makes it possible to design and manufacture lead frame of a semiconductor more efficiently.

• 마이크로전자및패키징학회지
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• 제27권1호
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• pp.1-7
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• 2020

The backside metallization process is typically used to attach a chip to a lead frame for semiconductor packaging because it has excellent bond-line and good electrical and thermal conduction. In particular, the backside metal with the Ag/Sn/Ag sandwich structure has a low-temperature bonding process and high remelting temperature because the interfacial structure composed of intermetallic compounds with higher melting temperatures than pure metal layers after die attach process. Here, we introduce a die attach process with the Ag/Sn/Ag sandwich structure to apply commercial semiconductor packages. After the die attachment, we investigated the evolution of the interfacial structures and evaluated the shear strength of the Ag/Sn/Ag sandwich structure and compared to those of a commercial backside metal (Au-12Ge).

• 한국지능정보시스템학회:학술대회논문집
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• 한국지능정보시스템학회 2001년도 The Pacific Aisan Confrence On Intelligent Systems 2001
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• pp.224-229
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• 2001

When a semiconductor package is assembled, various materials such as die attach adhesive, lead frame, EMC (Epoxy Molding Compound), and gold wire are used. For better preconditioning performance, the combination between the packaging materials by studying the compatibility of their properties as well as superior packaging material selection is important. But it is not an easy task to find proper packaging material sets, since a variety of factors like package design, substrate design, substrate size, substrate treatment, die size, die thickness, die passivation, and customer requirements should be considered. This research applies case-based reasoning(CBR) technique to solve this problem, utilizing prior cases that have been experienced. Our particular interests lie in building decision support model to aid the selection of proper die attach adhesive. The preliminary results show that this approach is promising.

• 반도체디스플레이기술학회지
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• 제22권3호
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• pp.1-7
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• 2023

Recently, in the semiconductor industry, memory device market is focusing on producing ultra-thin wafers for high integration. In the wafer manufacturing process, wafers after backgrinding and CMP process must be picked up as individual dies and subjected to be peeled off from the dicing tape. However, ultra-thin dies are vulnerable to the possibility of breakage and failure in their thickness and size. This research studies the mechanism of peeling a die with a high-aspect ratio using a thermopneumatic method instead of a die ejector with physical pins. Setting compressed air and the temperature as main factors, we determine the success of the digester using thermopneumatic system and analyze the good die to find the possibility of making mass-production equipment.

• 한국정밀공학회지
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• 제16권12호
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• pp.230-238
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• 1999

This paper describes a research work of developing computer-aided design of lead frame, semiconductor, with blanking operation which is very precise for progressive working. Approach to the system is based on the knowledge-based rules. Knowledge for the system is formulated from plasticity theories, experimental results and the empirical knowledge of field experts. This system has been written in AutoLISP on the AutoCAD using a personal computer and in I-DEAS Drafting Programming Language on the I-DEAS Master Series Drafting with Workstation, HP9000/715(64) and tool kit on the ESPRIT. Transference of data among AutoCAD, I-DEAS Master Series Drafting, and ESPRIT is accomplished by DXF(drawing exchange format) and IGES(initial graphics exchange specification) methods. This system is composed of six modules, which are input and shape treatment, production feasibility check, strip-layout, die-layout, modelling, and post-processor modules. The system can design process planning and Die design considering several factors and generate NC data automatically according to drawings of die-layout module. As forming process of high precision product and die design system using 2-D geometry recognition are integrated with technology of process planning, die design, and CAE analysis, standardization of die part in die design and process planning of high pression product for semiconductor lead frame is possible to set. Results carried out in each module will provide efficiencies to the designer and the manufacturer of lead frame, semiconductor.

• 한국정밀공학회지
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• 제16권3호통권96호
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• pp.25-29
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• 1999

The lead frame manufactured by press stamping process, is an important part of semiconductor. The recent technical trend of semiconductor, chip sized and high performance package technology, requires the lead frame to be of more multi-leads and of fine ILP (Inner Lead Pitch). As the ILP is getting finer, its corresponding punch of the stamping die is getting narrower. The punch narrower than its stamping limit has been broken due to local buckling. This paper analyzed the phenomena of punch breakdown. Moreover, the punch design was modified to increase the critical limit of buckling force. This paper, also, suggested new design rules of the punch, which asks the modification of its lead frame design that has to be considered in the stage of semiconductor package design. The new design rules of lead frame design yields a good reliability of semiconductor package as well as a good quality of lead frame.

• 대한산업공학회지
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• 제29권2호
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• Design & Manufacturing
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• 제8권1호
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• pp.27-30
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• 2014

Alloy tool steel such as SKD11 and SKD61 or high speed tool like SKH51 are used as materials for semiconductor dies. Cavities, curl blocks, pot blocks and housings are made from those materials. To make those parts from alloy tool steel or high speed tool, one utilizes discharge machining, and mechanical machining including machining center, milling, drilling, forming grinding and others. In the process of cutting machining and polishing, the die materials become unsuitable for machining owing to bubbles and foreign substances in them, which hinders production process. Therefore, this study focuses on die material selection criteria, and on analysis and comparison of material characteristics to help companies to solve their problems, make die manufacture less burdensome and extend die life.

• 반도체디스플레이기술학회지
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• 제20권4호
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• pp.171-176
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• 2021

Die-to-wafer (D2W) hybrid bonding in the multilayer semiconductor manufacturing process is one of wafer direct bonding, and various studies are being conducted around the world. A noteworthy point in the current die-to-wafer process is that a lot of voids occur on the bonding surface of the die during bonding. In this study, as a suggested method for removing voids generated during the D2W hybrid bonding process, a flexible mechanism for implementing convex for die bonding to be applied to the bond head is proposed. In addition, modeling of flexible mechanisms, analysis/design/control/evaluation of static/dynamics properties are performed. The proposed system was controlled by capacitive sensor (lion precision, CPL 290), piezo actuator (P-888,91), and dSpace. This flexure mechanism implemented a working range of 200 ㎛, resolution(3σ) of 7.276nm, Inposition(3σ) of 3.503nm, settling time(2%) of 500.133ms by applying a reverse bridge type mechanism and leaf spring guide, and at the same time realized a maximum step difference of 6 ㎛ between die edge and center. The results of this study are applied to the D2W hybrid bonding process and are expected to bring about an effect of increasing semiconductor yield through void removal. In addition, it is expected that it can be utilized as a system that meets the convex variable amount required for each device by adjusting the elongation amount of the piezo actuator coupled to the flexible mechanism in a precise unit.