• 한국진공학회:학술대회논문집
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• 한국진공학회 1998년도 제14회 학술발표회 논문개요집
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• pp.20-20
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• 1998

I Ion beam technology has recently attracted much interest because it has exciting t technological p아:ential for surface analysis, ion beam mixing, surface cleaning and etching i in thin film growth and semiconductor fabrication processes, etc. Es야~cially, ion beam s sputtering has been widely used for sputter depth profiling with x-photoelectron S spectroscopy (XPS) , Auger electron s$\pi$~troscopy(AES), and secondary-ion mass S야i따oscopy(SIMS). However, The problem of surface compositional ch없1ge due to ion b bombardment remains to be understo여 없ld solved. So far sputtering processes have been s studied by s따face an외ysis tools such as XPS, AES, and SIMS which use the sputtering p process again. It would be improbable to measure the modified surface composition profiles a accurately due to ion beam bombardment with surface analysis techniques based on sputter d depth profiling. However, recently Medium energy ion scattering spectroscopy(MEIS) has b been applied to study the sputtering of solid surface at ion bombardment and has been p proved that it has been extremely valuable in probing the surface composition 뻐d s structure nondestructively and quantita디vely with less than 1.0 nm depth resolution. To u understand the sputtering processes of solid surface at ion bombardment, The Molecular D Dynamics(MD) and Monte Carlo(MC) simulation has been used and give an intimate i insight into the sputtering processes of solid surfaces. In this presentation, the sputtering processes of alloys and compound samples at ion b bombardment will be reviewed and the MEIS results for the Ar+ sputter induced altered l layer of the TazOs thin film 뻐dd없nage profiling of Ar+ ion sputt얹"ed Si(100) surface will b be discussed with the results of MD and MC simulation.tion.

• Korean Chemical Engineering Research
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• 제49권4호
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• pp.485-490
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• 2011

사불화탄소($CF_4$)는 반도체 제조공정에서 에칭과 반응기 세척에서 사용되어온 가스이다. $CF_4$는 적외선을 강하게 흡수하고 대기 중 잔류시간이 길어서 지구온난화에 영향을 미치기 때문에 고효율의 분해가 필요하다. 본 연구에서는 플라즈마와 워터젯을 결합하여 워터젯 글라이딩 아크 플라즈마 시스템을 개발하고, 이를 이용하여 $CF_4$를 고효율로 분해할 수 있도록 방전영역을 증가시키고 다량의 OH 라디칼을 생성시킬 수 있는 최적의 조업 조건을 결정하였다. 공정 실험 변수로는 워터젯 주입량, $CF_4$ 초기 농도, 전체 가스량과 주입에너지량(SEI : Specific energy input)을 선정하였다. 변수실험을 통하여 워터젯 주입량이 25.5 mL/min, $CF_4$ 초기 농도 2.2%, 전체 가스량 9.2 L/min, SEI 7.2 kJ/L일 때 $CF_4$ 분해율은 최고 97%까지 도달하였다.

• 한국표면공학회지
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• 제32권3호
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• pp.239-243
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• 1999

At Present, 200mm wafer technology is being applied for commercial fabrications of 64, 128, and 256 M DRAM devices, and 300mm technology will be evolved for 1G DRAM devices in the early 21th century, recognizing limitations of several process technologies. In particular recognition has been realized in harmful effects of surface contamination of trace metals introduced during devicing processes. Such a guide line for surface metal contamination has been proposed as 1E9 and 1E10 atoms/$\textrm{cm}^2$ of individual metal contamination for wafering and devicing of 1G DRAM, respectively, and so its measurement limit should be at least 1E8 atoms/$\textrm{cm}^2$. The detection limit of present measurement systems is 2E9 atoms/$\textrm{cm}^2$ obtainable with TRXFA(Total Reflection X-Ray Fluorescence Analysis). TRXFA is nondestructive and the simplest in terms of operation, and it maps the whole wafer surfaces but needs detection improvement. X-Ray intensity produced with synchrotron accelerator is much higher than that of conventional X-ray sources by order of 4-5 magnitudes. Hence theoretically its reactivity with silicon surfaces is expected to be much higher than the conventional one, realizing improvement of detection limit. X-ray produced with synchrotron accelerator is illuminated at a very low angle with silicon wafer surfaces such as 0.1 degree and reflects totally. Hence informations only from surface can be collected and utilized without overlapping with bulk informations. This study shows the total reflection phenomenon and quantitative improvement of detection limit for metallic contamination. It is confirmed that synchrotron X-ray can be a very promising alternative for realizing improvement of detection limit for the next generation devices.

• Tribology and Lubricants
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• 제35권5호
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• pp.274-285
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• 2019

Chemical mechanical polishing (CMP), which is a material removal process involving chemical surface reactions and mechanical abrasive action, is an essential manufacturing process for obtaining high-quality semiconductor surfaces with ultrahigh precision features. Recent rapid growth in the industries of digital devices and semiconductors has accelerated the demands for processing of various substrate and film materials. In addition, to solve many issues and challenges related to high integration such as micro-defects, non-uniformity, and post-process cleaning, it has become increasingly necessary to approach and understand the processing mechanisms for various substrate materials and abrasive particle behaviors from a tribological point of view. Based on these backgrounds, we review recent CMP R&D trends in this study. We examine experimental and analytical studies with a focus on substrate materials and abrasive particles. For the reduction of micro-scratch generation, understanding the correlation between friction and the generation mechanism by abrasive particle behaviors is critical. Furthermore, the contact stiffness at the wafer-particle (slurry)-pad interface should be carefully considered. Regarding substrate materials, recent research trends and technologies have been introduced that focus on sapphire (${\alpha}$-alumina, $Al_2O_3$), silicon carbide (SiC), and gallium nitride (GaN), which are used for organic light emitting devices. High-speed processing technology that does not generate surface defects should be developed for low-cost production of various substrates. For this purpose, effective methods for reducing and removing surface residues and deformed layers should be explored through tribological approaches. Finally, we present future challenges and issues related to the CMP process from a tribological perspective.

• 한국산학기술학회논문지
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• 제19권1호
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• pp.603-608
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• 2018

전압 인가식 제전방식이 반도체나 디스플레이 산업에는 가장 많이 사용되고 있지만, 방전에 의한 주변 미세 먼지의 흡착 및 전극핀의 오염으로 불량 발생의 원인을 제공하므로, 주기적인 관리 비용이 발생하게 된다. 전극핀의 오염 문제는 코로나 방전으로 인하여, 주변 공기의 미세한 입자를 축적함으로 생성된다. Fuzz ball의 생성은 전극핀의 마모를 촉진 시키고, 또한 정전기 제거 장치의 성능을 저하시킨다. 오염물 제거 방법은 수동 브러쉬 및 자동 브러쉬를 이용하여 기계적인 세척 방법이 효과적이지만, 추가적인 기계부품이나 사용자의 관리를 요구한다. 일부의 경우에는 이미터에 축척된 오염물이 웨이퍼나 제품에 전이될 수도 있다. 이러한 문제를 해결하기 위해, 제전기의 외부로 돌출되는 전극핀을 없애고, 이온탱크 내부에 위치한 텡스텐 전극선을 이용하여 주위 기체 분자를 직접 이온화할 수 있는 청정 환경에 적합한 정전기 제거 장치를 개발하였다. 한국기계연구원에서 시험인증한 결과, 오염 입자는 평균 $0.7572particles/ft^3$이고, 제전 시간은 2초 이하 이며, 잔류 전위는 7.6V로 만족할 만한 결과를 얻었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.150.1-150.1
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• 2014

Showerhead is used as a main part in the semiconductor equipment. The face plate flatness should remain constant and the cleaning performance must be gained to keep the uniformity level of etching or deposition in chemical vapor deposition process. High operating temperature or long period of thermal loading could lead the showerhead to be deformed thermally. In some case, the thermal deformation appears very sensitive to showerhead performance. This paper describes the methods for robust design using computational fluid dynamics. To reveal the influence of the post distribution on flow pattern in the showerhead cavity, numerical simulation was performed for several post distributions. The flow structure appears similar to an impinging flow near a centered baffle in showerhead cavity. We took the structure as an index to estimate diffusion path. A robust design to reduce the thermal deformation of showerhead can be achieved using post number increase without ill effect on flow. To prevent the showerhead deformation by heat loading, its face plate thickness was determined additionally using numerical simulation. The face plate has thousands of impinging holes. The design key is to keep pressure drop distribution on the showerhead face plate with the holes. This study reads the methodology to apply to a showerhead hole design. A Hagen-Poiseuille equation gives the pressure drop in a fluid flowing through such hole. The assumptions of the equation are the fluid is viscous-incompressible and the flow is laminar fully developed in a through hole. An equation can be expressed with radius R and length L related to the volume flow rate Q from the Hagen-Poiseuille equation, $Q={\pi}R4{\Delta}p/8{\mu}L$, where ${\mu}$ is the viscosity and ${\Delta}p$ is the pressure drop. In present case, each hole has steps at both the inlet and the outlet, and the fluid appears compressible. So we simplify the equation as $Q=C(R,L){\Delta}p$. A series of performance curves for a through hole with geometric parameters were obtained using two-dimensional numerical simulation. We obtained a relation between the hole diameter and hole length from the test cases to determine hole diameter at fixed hole length. A numerical simulation has been performed as a tool for enhancing showerhead robust design from flow structure. Geometric parameters for the design were post distribution and face plate thickness. The reinforced showerhead has been installed and its effective deposition profile is being shown in factory.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• 마이크로전자및패키징학회지
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• 제6권4호
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• pp.1-7
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• 1999

MCM-D 기판에 수동소자를 내장시키는 공정을 개발하였다. MCM-D 기판은 Cu/감광성 BCB를 각각 금속배선 및 절연막 재료로 사용하였고, 금속배선은 Ti/cu를 각각 1000$\AA$/3000$\AA$으로 스퍼터한 후 fountain 방식으로 전기 도금하여 3 um Cu를 형성하였으며, BCB 층에 신뢰성있는 비아형성을 위하여 BCB의 공정특성과 $C_2F_6$를 사용한 플라즈마 cleaning영향을 AES로 분석하였다. 이 실험에서 제작한 MCM-D 기판은 절연막과 금속배선 층이 각각 5개, 4개 층으로 구성되는데 저항은 2번째 절연막 위에 thermal evaporator 방식으로 NiCr을 600$\AA$증착하여 시트저항이 21 $\Omega$/sq가 되게 형성하였고. 인덕터는 coplanar 구조로 3, 4번째 금속배선층에 형성하였으며, 커패시터는 절연막으로 PECVD $Si_3N_4$를 900$\AA$증착한 후 1, 2번째 금속배선층에 형성하여 88nF/$\textrm {cm}^2$의 커패시턴스를 얻었다. 이 공정은 PECVD $Si_3N_4$와 thermal evaporation NiCr 공정을 이용함으로써 기존의 반도체 공정을 이용하여 MCM-D 기판에 수동소자를 안정적으로 내장시킬 수 있었다.

• 한국산업보건학회지
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• 제34권1호
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• pp.18-25
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• 2024

Objectives: The primary aim of this study is to create an Occupational Safety and Health (OSH) guide for high-risk maintenance tasks, specifically one designed for maintenance work (MW) in the electronics industry. Methods: The methodology involved a literature review, field investigations, and discussions. An initial draft of the OSH guide was created and then refined through consultations with experts possessing extensive experience in MW for electronic processes. Results: Specific MW tasks within electronics processing facilities identified as high-risk by the research were selected. A comprehensive OSH guide for these tasks was developed consisting of approximately 11 to 12 components and encompassing about 20-25 pages. Implementing safety and health measures before, during, and after MW is crucial for the protection of maintenance personnel. The guide is enriched with real-case scenarios of industrial accidents and occupational diseases to enhance maintenance workers' comprehension of the OSH principles. For a clearer understanding of and adherence to the safety protocols, the guide incorporates visual aids, including cartoons and photographs. Conclusions: This OSH guide is designed to ensure the protection of workers involved in maintenance activities in the electronics industry. It aligns with global standards set by the International Organization for Standardization (ISO) and Semiconductor Equipment and Material International (SEMI) to ensure a high level of safety and compliance.