• Proceedings of the Materials Research Society of Korea Conference
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• 2007.11a
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• pp.47.1-47.1
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• 2007

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.534-537
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• 1998

In this paper, a set of novel self-timed latches are introduced and analyzed. These latches have no back-to-back connection as in conventional self-timed latch, and both inverting and noninerting outputs are evaluated simultaneously leading to thigher oepating frequencies. Power consumption of these latches ar ealso comparable to or less than that of conventional circuits. Novel type of cross-coupled inverter used in the proosed circuits implements static operatin without signal fighting with the main driver during signal transition. Proposed latches ar tested using a 0.6.mu.m triple-poly triple-metal n-well CMOS technology. The resutls indicates that proposed active-low sefl-timed latch (ALSTL) improves speed by 14-34% over conventional NAND SR latch, while in active-high self-timed latch (AHSTL) the improvements are 15-35% with less power as compared with corresponding NORA SR latch. These novel latches have been successfully implemented in a high-speed synchronous DRAM (SDRAM).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.223-223
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• 2007

Thermal and mechanical properties were investigated in several semi-conductive materials which is composed of carbon black and polymer. EVA, EEA, and EBA is normally used for matrix polymer and normally acetylene black and furnace black is used. Isothermal thermo gravimetric analysis is done as a function of atmosphere and temperature. In nitrogen atmosphere semicon compound was slowly degradaded but in ambient condition degradaded fast. So in the cable manufacturing, atmosphere and materials are very important.

• Proceedings of the Korean Vacuum Society Conference
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• 1995.06a
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• pp.149-149
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• 1995

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.11
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• pp.1274-1281
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• 1988

A new voltage-controlled oscillator based on a voltage-controlled integrator has been developed. It consists of a Schmitt-trigger and a voltage-controlled integrator, which is realized by an operational transconductance amplifier (OTA) and a grounded capacitor. The input control voltage changes the time constant of the integrator, and hence the oscillation frequency. The SPICE simulation shows that a prototype circuit, which oscillates at 12.21 KHz at 0 V, has the conversion sencitivity 2,437 Hz/V and the residual nonlinearity less than 0.68% in a control voltage range from -2 V to 2 V. It also shows that the circuit provides a temperature drift less than + 250 ppm/$^{\circ}$C for frequencies up to 100 KHz.

• Journal of the Korean Applied Science and Technology
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• v.16 no.1
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• pp.105-115
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• 1999

P-type의 단결정 실리콘 위에 $1000{\AA}$의 열산화막을 성장시킨후 $5500{\AA}$의 다결정 실리콘으로 증착된 시료를 가지고 $HBr/Cl_2/He-O_2$ 혼합기체로 식각할 때 시료의 식각 특성에 관한 $H_2-O_2$ 기체함량. RF 전력, 압력에 대한 영향을 XPS(X-ray photoelectron Spectroscopy)와 SEM(Scanning Electron Microscopy)으로 조사하였다. $HBr/Cl_2/He-O_2$ 혼합기체로 식각되는 동안 형성된 다결정 실리콘 식각속도는 $H_2-O_2$ 함량 증가에 따라 증가하였으며 식각잔유물은 RF 전력과 압력변화에 의해 영향은 받지 않는 것으로 나타났으며, 다결정 실리콘 측벽에서의 증착속도는 낮은 RF전력과 높은 압력에서 높게 나타났다. 다결정 실리콘 식각 잔유물의 결합에너지는 안정한 $SiO_2$인 열산화막의 경우보다 높으므로 식각 잔유물은 $SiO_{\chi}({\chi}>2)$의 화합결합을 가지는 산화물과 같은 잔유물로 생각된다.

• Journal of the Korea Safety Management & Science
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• v.15 no.3
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• pp.171-175
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• 2013

It has passed 10 years to enact 'Act on Special Measures for the Promotion of Venture Businesses.' With 10 years' data book, we study to find the correlation between venture investment and start-up. According to correlation analysis, we find that venture investment and start-up are strong and positive-related, and the increment of investment can contribute to the increment of start-up.

• Journal of the Korea Safety Management & Science
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• v.15 no.4
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• pp.401-405
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• 2013

Fund-raising is critical to start-up and early stage company. We try to analyse a status of fund-raising in start-up and early stage company, and a correlation between angel investment and start-up. With last 10 years' data sheets, we find that angel investment is not related with start-up fund raising.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1021-1024
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• 1998

Computer-aided design of VLSI circuits is usually carried out in three synthesis steps; high-level synthesis, logic synthesis and layout synthesis. Each synthesis step is further kroken into a few optimization problems. In this paper we study the area minimization problem in floorplanning(also known as the floorplan sizing problem). We propose the area minimization algorithms for general floorplans.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.867-870
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• 1998

In this paper we simulated 0.30um NMOS transitor to analysis hot carrier degradation depend on As, As+P, P LDD structure. As a result we obtained As+P LDD structure was good hot carrier immunity. Also we find that hog carrier life time improved a sincresing P dose due to P dose helps in grading the nLDD junction. However As-only junction was poor due to junction high peak position located near the surface.