• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.702-705
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• 2003

We reported the result of driving PDP's in selective erase scheme and three wall charge states. Compared to the selective write driving scheme, the selective erase scheme achieved flicker free half-ON state with much simpler driving waveforms than the selective write scheme. We believed that this improvement was possible since the cells entering the address period with enough wall charges to modulate easily with.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.12
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• pp.2189-2195
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• 2007

In this paper, we propose a newly developed selective reset waveform of a ac PDP using the wide erase pulse technique with the control of address bias voltage. Although it is generally understood that the wide pulse erasing methode shows the narrow driving margin in an opposite discharge type ac PDP, we could obtain a moderate driving margin in a 3-electrode surface discharge type ac PDP. The obtained driving margin shows a strong dependency on the sustain voltage and the address bias voltage. The lower the sustain and the address bias voltage, the wider the driving margin. The pulse width of the proposed waveform is only $10{\mu}s$, which gives additional time to the sustain period, hence increases the brightness. The brightness and contrast ratio increase about 20% together comparing to the conventional ramp type selective reset waveform with the driving scheme of 10 subfield ADS method. The driving margin was measured with the line by line addressed pattern on the white test panel of 2inch diagonal size and the discharge gas was Ne+Xe4%, 400torr.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.7-11
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• 2017

In this paper, we have studied the characteristics of NAND Flash memory in SONOS Poly-Si Thin Film Transistor (Poly-Si TFT) device. Source/drain junctions(S/D) of cells were not implanted and selective transistors were located in the end of cells. We found the optimum conditions of process by means of the estimation for the doping concentration of channel and source/drain of selective transistor. As the doping concentration was increased, the channel current was increased and the characteristic of erase was improved. It was believed that the improvement of erase characteristic was probably due to the higher channel potential induced by GIDL current at the abrupt junction. In the condition of process optimum, program windows of threshold voltages were about 2.5V after writing and erasing. In addition, it was obtained that the swing value of poly Si TFT and the reliability by bake were enhanced by increasing process temperature of tunnel oxide.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.225-227
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• 2000

LGE developed and demonstrated the first 60-inch full color AC plasma display panel with the 1365 ${\times}$ 768 resolution. Both Sol-gel and E-beam method have been tried for MgO layer, and photolithography has been used for electrodes and phosphor layer to fabricate a 60-inch panel. Selective Erase, Selective Write, Address Display Separate, and Address While Display driving scheme have been tested. Its luminance and contrast ratio is about $550\;cd/m^2$ and 500:1, respectively.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.152-154
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• 2005

This paper proposes the new subfield method to erase reverse gray levels and low gray level contour in AC plasma display panel(PDP). In the conventional method, it is supposed that output luminance levels of a PDP increase regularly. But actual output luminance levels of a PDP increase irregularly. Therefore, conventional methods are unable to effectively reduce low gray-level contours and reverse gray levels. Accordingly, a new subfield method is applied to improve the low gray-level expression in PDP. Conclusively this paper clear proof that a new subfield method can suppress low gray-level contours and reverse gray levels more effectively than conventional methods.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.706-709
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• 2003

We made an optimization effort on driving waveforms for the Quantized Memory Addressing (QMA) in selective write mode of operation. It was necessary to add long ramp type erase pulses after the total write pulse and the sustain period to obtain stable intermediate luminance discharges. Furthermore, fast rising ramp type total write as well as two step addressing scheme were adopted for better discharge stability.

• Proceedings of the KIEE Conference
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• 2003.10a
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• pp.258-260
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• 2003

In this paper, we study the reduction of the Dynamic False Contour in a new driving method. This method divides scan lines into Multi Blocks, and drives both selective write and selective erase address. Because of the characteristic of proposed waveform, each scan line has a different sustain pulse weight. Therefore, the Dynamic False Contour occurs seriously in the boundary of each Block. Finally, if scan-lines tie several lines, the Dynamic False Contour can reduce in the boundary of each Block.