• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.11
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• pp.1470-1476
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• 2020

This paper describes a design of a lightweight security system-on-chip (SoC) suitable for the implementation of security protocols for IoT and mobile devices. The security SoC using Cortex-M0 as a CPU integrates hardware crypto engines including an elliptic curve cryptography (ECC) core, a SHA3 hash core, an ARIA-AES block cipher core and a true random number generator (TRNG) core. The ECC core was designed to support twenty elliptic curves over both prime field and binary field defined in the SEC2, and was based on a word-based Montgomery multiplier in which the partial product generations/additions and modular reductions are processed in a sub-pipelining manner. The H/W-S/W co-operation for elliptic curve digital signature algorithm (EC-DSA) protocol was demonstrated by implementing the security SoC on a Cyclone-5 FPGA device. The security SoC, synthesized with a 65-nm CMOS cell library, occupies 193,312 gate equivalents (GEs) and 84 kbytes of RAM.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.05a
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• pp.63-65
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• 2021

This paper describes an integrated H/W-S/W implementation of elliptic curve digital signature algorithm (EC-DSA) using a security system-on-chip (SoC). The security SoC uses the Cortex-A53 APU as CPU, and the hardware IPs of high-performance elliptic curve cryptography (HP-ECC) core and SHA3 (secure hash algorithm 3) hash function core are interfaced via AXI4-Lite bus protocol. The signature generation and verification processes of EC-DSA were verified by the implementation of the security SoC on a Zynq UltraScale+ MPSoC device.

• ETRI Journal
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• v.25 no.6
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• pp.510-516
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• 2003

In this paper, we describe the development of a platform-based SoC of a 32-bit smart card. The smart card uses a 32-bit microprocessor for high performance and two cryptographic processors for high security. It supports both contact and contactless interfaces, which comply with ISO/IEC 7816 and 14496 Type B. It has a Java Card OS to support multiple applications. We modeled smart card readers with a foreign language interface for efficient verification of the smart card SoC. The SoC was implemented using 0.25 ${\mu}m$ technology. To reduce the power consumption of the smart card SoC, we applied power optimization techniques, including clock gating. Experimental results show that the power consumption of the RSA and ECC cryptographic processors can be reduced by 32% and 62%, respectively, without increasing the area.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.251-253
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• 2019

This paper describes an implementation of a security SoC (System-on-Chip) prototype that interfaces a microprocessor with a block cipher crypto-core. The Cortex-M0 was used as a microprocessor, and a crypto-core implemented by integrating ARIA and AES into a single hardware was used as an intellectual property (IP). The integrated ARIA-AES crypto-core supports five modes of operation including ECB, CBC, CFB, CTR and OFB, and two master key sizes of 128-bit and 256-bit. The integrated ARIA-AES crypto-core was interfaced to work with the AHB-light bus protocol of Cortex-M0, and the crypto-core IP was expected to operate at clock frequencies up to 50 MHz. The security SoC prototype was verified by BFM simulation, and then hardware-software co-verification was carried out with FPGA implementation.

• Korean Security Journal
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• no.4
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• pp.319-341
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• 2001

Most of protecting security activity is carried out by manpower partly by security equipment. The protecting security market and the area of protecting security activity is increasing in spite of change of economic and social environment situation. For more effective protecting security activity, the coordination of electronic equipment and manpower is required. So some application method is suggested throughout the thesis, which is especially focused on new approaching method. The integration of intrusion detecting system, C.C.TV system and Access control system is introduced for general application in chapter III, and some application systems are proposed for protecting security activity in chapter IV. But the security equipment is only aid for manpower, so manpower and equipment should be coordinated well.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

• Journal of IKEEE
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• v.23 no.2
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• pp.388-394
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• 2019

This paper describes a design of security system-on-chip (SoC) that integrates a Cortex-M0 CPU with an AAW (ARIA-AES- Whirlpool) crypto-core which implements two block cipher algorithms of ARIA and AES and a hash function Whirlpool into an unified hardware architecture. The AAW crypto-core was implemented in a small area through hardware sharing based on algorithmic characteristics of ARIA, AES and Whirlpool, and it supports key sizes of 128-bit and 256-bit. The designed security SoC was implemented on FPGA device and verified by hardware-software co-operation. The AAW crypto-core occupied 5,911 slices, and the AHB_Slave including the AAW crypto-core was implemented with 6,366 slices. The maximum clock frequency of the AHB_Slave was estimated at 36 MHz, the estimated throughputs of the ARIA-128 and the AES-128 was 83 Mbps and 78 Mbps respectively, and the throughput of the Whirlpool hash function of 512-bit block was 156 Mbps.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.5
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• pp.97-107
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• 2004

This paper presents an System-on-Chip(SoC) implementation of fingerprint feature extraction system. Typical fingerprint feature extraction systems employ binarization and thinning processes which cause many extraction errors for low qualify fingerprint images and degrade the accuracy of the entire fingerprint recognition system. To solve these problems, an algorithm directly following ridgelines without the binarization and thinning process has been proposed. However, the computational requirement of the algorithm makes it hard to implement it on SoCs by using software only. This paper presents an implementation of the ridge-following algorithm onto SoCs. The algorithm has been modified to increase the efficiency of hardwares. Each function block of the algorithm has been implemented in hardware or in software by considering its computational complexity, cost and utilization of the hardware, and efficiency of the entire system. The fingerprint feature extraction system has been developed as an IP for SoCs, hence it can be used on many kinds of SoCs for smart cards.

• Journal of Internet Computing and Services
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• v.22 no.6
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• pp.91-97
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• 2021

The United States is responding to evolving cyberattacks through the Commercial Solutions for Classified Program (CSfC). Authorized safety evaluation and certification are being carried out so that US government agencies can quickly introduce civilian commercial security products into the national pavilion. Commercial security products registered in the CSfC process can be used by defense agencies through a rapid approval process. Defense agencies approve commercial security products without duplicate evaluation. Approved security products can reduce the time, cost, and cost of the approval process required to implement the defense information system. In this study, security control for 4 types of network security architecture MSC (Multi-Site Connectivity), MA (Mobile Access), Campus WLAN, and DAR (Data at Rest) proposed by the US National Security Agency (NSA) for introduction to national defense A detailed analysis was performed on the items.

• Korean Security Journal
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• no.8
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• pp.281-308
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• 2004

With regard to problems related to qualification of Private Security, this study is qualitatively to develop education & training program from the viewpoint of education for the purpose of checking professionalism of Security guard. Offering the solutions for improvement by analyzing problems of articles related to training for Private Security guard prescribed in existing 'Law of Guarding', I made studies of development of practical affairs-centered education & training program for Private Security guard on the basis of Private Security guard' duties. Education & training program for Private Security guard must be made up of practical affairs-centered one related to concrete duties. Also because it needs to be made on the basis of a model planned for the program with combined method, this study gave example of model and contests of education & training program based on duties of Facilities Security. Main duties of cPrivate Security guard can be divided into four duties; duties on their own posts, patrolling, control of going in and out, dealing with accidents and so on. Private Security guard are given main duties by each post, and after adjusting conditions according to personnel organization, they perform their own duties. As education & training program based on Private Security guard' duties, common education & training program for the new-appointed, practical affairs-centered education & training program, education & training program for superintendents, service education & training program and so on are provided.