• Title/Summary/Keyword: Security Authentication Bit

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A Study on the Design and the Performance Improvement of IP Access Control Protocol for External Mobile terminal (외부 이동단말의 접근제어를 위한 IP 프로토콜 설계 및 성능 개선에 관한 연구)

  • 박대우
    • Journal of the Korea Society of Computer and Information
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    • v.9 no.2
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    • pp.41-48
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    • 2004
  • Access control protocol have verified security of external mobile terminal that access to inner information sever at Ubiquitous ages. In this paper, I would design for If Access Control Protocol of considering operation time when make cipher digital signature. Public key are used Individual identification number that issued from certify communication company, and cipher algorithm are used ECDSA definition factor for generation and verification of digital signature and it used Elliptic Curve with over 160 bit Key. Also, Access control operate on If level that designed IPv6 frame architecture. I would conclude that IP Access Control Protocol have verified security and improved performance in operation time more 4 times than before protocols when through the communication of use cipher digital signature for authentication and verification.

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Development of 3-State Blind Digital Watermark based on the Correlation Function (신호상관함수를 이용한 3 상태 능동적 디지털 워터마크의 개발)

  • Choi, YongSoo
    • Journal of Software Assessment and Valuation
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    • v.16 no.2
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    • pp.143-151
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    • 2020
  • The digital content's security and authentication are important in the field of digital content application. There are some methods to perform the authentication. The digital watermarking is one of authentication methods. Paper presents a digital watermark authentication method that works in the application of digital image. The proposed watermark has the triple status information and performs the embedding and the detection without original Content. When authenticating the owner information of digital content, an autocorrelation function is used. In addition, a spread spectrum method is used to be adaptive to the signal of the original content in the frequency domain(DWT Domain). Therefore, the possibility of errors occurring in the detection of hidden information was reduced. it also has a advantage what Watermarking in DWT has faster embedding and detection time than other transformation domains(DFT, DCT, etc.). if it has a an image of size N=mXm, the computational amount can be reduced from O(N·logN) to O(N). The particular advantage is that it can hide more information(bits) per bit.

Efficient authenticate protocol for very Low-Cost RFID (저가형 RFID 시스템을 위한 효율적인 인증 프로토콜)

  • Choi Eun Young;Choi Dong Hee;Lim Jong In;Lee Dong Hoon
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.15 no.5
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    • pp.59-71
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    • 2005
  • A RFID (Radio Frequency Identification) system receives attention as the technology which can realize the ubiquitous computing environment. However, the feature of the RFID tags may bring about new threats to the security and privacy of individuals. Recently, Juels proposed the minimalist cryptography for very low-cost RFID tags, which is secure. but only under the impractical assumption such that an adversary is allowed to eavesdrop only the pre-defined number of sessions. In this paper, we propose a scheme to protect privacy for very low-cost RFID systems. The proposed protocol uses only bit-wise operations without my costly cryptographic function such as hashing, encryption which is secure which is secure against an adversary who is allowed to eavesdrop transmitted message in every session any impractical assumption. The proposed scheme also is more efficient since our scheme requires less datas as well as few number of computations than Juels's scheme.

Copyright Protection using Encryption of DCT Coefficients and Motion Vector in Video Codec of Mobile Device (모바일 기기내의 비디오 코덱에서 DCT 계수와 움직임 벡터의 암호화를 이용한 저작권 보호)

  • Kwon, Goo Rak;Kim, Young Ro
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.4 no.1
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    • pp.41-46
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    • 2008
  • With widespread use of the Internet and improvements in streaming media and compression technology, digital music, video, and image can be distributed instantaneously across the Internet to end-users. However, most conventional Digital Right Management are often not secure and fast enough to process the vast amount of data generated by the multimedia applications to meet the real-time constraints. In this paper, we propose the copyright protection using encryption of DCT coefficients and motion vector in MPEG-4 video codec of mobile device. This paper presents a new Digital Rights Management that modifies the Motion Vector of Macroblock for mobile device. Experimental results indicate that the proposed DRM can not only achieve very low cost of the encryption but also enable separable authentication to individual mobile devices such as Portable Multimedia Player and Personal Digital Assistants. The performance of the proposed methods have low complexity and low increase of bit rate in overhead.

An Efficient Hardware Implementation of AES-based CCM Protocol for IEEE 802.11i Wireless LAN Security (IEEE 802.11i 보안용 AES 기반 CCM 프로토콜의 효율적인 하드웨어로 구현)

  • Hwang, Seok-Ki;Lee, Jin-Woo;Kim, Chay-Hyeun;Song, You-Su;Shin, Kyung-Wook
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.591-594
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    • 2005
  • This paper describes a design of AES-based CCM Protocol for IEEE 802.11i Wireless LAN Security. The CCMP core is designed with 128-bit data path and iterative structyre which uses 1 clock cycle per round operation. To maximize its performance, two AES cores are used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining) mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about 23% compared with conventional LUT-based design. The CCMP core designed in Verilog-HDL has 35,013 gates, and the estimated throughput is about 768Mbps at 66-MHz clock frequency.

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An Area-efficient Design of SHA-256 Hash Processor for IoT Security (IoT 보안을 위한 SHA-256 해시 프로세서의 면적 효율적인 설계)

  • Lee, Sang-Hyun;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.22 no.1
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    • pp.109-116
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    • 2018
  • This paper describes an area-efficient design of SHA-256 hash function that is widely used in various security protocols including digital signature, authentication code, key generation. The SHA-256 hash processor includes a padder block for padding and parsing input message, so that it can operate without software for preprocessing. Round function was designed with a 16-bit data-path that processed 64 round computations in 128 clock cycles, resulting in an optimized area per throughput (APT) performance as well as small area implementation. The SHA-256 hash processor was verified by FPGA implementation using Virtex5 device, and it was estimated that the throughput was 337 Mbps at maximum clock frequency of 116 MHz. The synthesis for ASIC implementation using a $0.18-{\mu}m$ CMOS cell library shows that it has 13,251 gate equivalents (GEs) and it can operate up to 200 MHz clock frequency.

Security Analysis of the Whirlpool Hash Function in the Cloud of Things

  • Li, Wei;Gao, Zhiyong;Gu, Dawu;Ge, Chenyu;Liao, Linfeng;Zhou, Zhihong;Liu, Ya;Liu, Zhiqiang
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.11 no.1
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    • pp.536-551
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    • 2017
  • With the advancement and deployment of leading-edge telecommunication technologies for sensing and collecting, computing related information, Cloud of Things (CoTs) has emerged as a typical application platform that is envisioned to revolutionize the daily activities of human society, such as intelligent transportation, modern logistics, food safety, environmental monitoring, etc. To avoid any possible malicious attack and resource abuse, employing hash functions is widely recognized as one of the most effective approaches for CoTs to achieve message integrity and data authentication. The Whirlpool hash function has served as part of the joint ISO/IEC 10118-3 International Standard by the International Organization for Standardization (ISO) and the International Electrotechnical Commission (IEC). In this paper, we propose an effective differential fault analysis on Whirlpool in the byte-oriented random fault model. The mathematical analysis and experimental results show that 8 random faults on average are required to obtain the current 512-bit message input of whirlpool and the secret key of HMAC-Whirlpool. Our work demonstrates that Whirlpool and HMAC-Whirlpool are both vulnerable to the single byte differential fault analysis. It provides a new reference for the security analysis of the same structure of the hash functions in the CoTs.

A Design of HAS-160 Processor for Smartcard Application (스마트카드용 HAS-160 프로세서 설계)

  • Kim, Hae-ju;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2009.10a
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    • pp.913-916
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    • 2009
  • This paper describes a hardware design of hash processor which implements HAS-160 algorithm adopted as a Korean standard. To achieve a high-speed operation with small-area, the arithmetic operation is implemented using a hybrid structure of 5:3 and 3:2 carry-save adders and a carry-select adder. The HAS-160 processor synthesized with $0.35-{\mu}m$ CMOS cell library has 17,600 gates. It computes a 160-bit hash code from a message block of 512 bits in 82 clock cycles, and has 312 Mbps throughput at 50 MHz@3.3-V clock frequency.

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A Small-Area Hardware Implementation of Hash Algorithm Standard HAS-160 (해쉬 알고리듬 표준 HAS-l60의 저면적 하드웨어 구현)

  • Kim, Hae-Ju;Jeon, Heung-Woo;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.3
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    • pp.715-722
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    • 2010
  • This paper describes a hardware design of hash function processor which implements Korean Hash Algorithm Standard HAS-160. The HAS-160 processor compresses a message with arbitrary lengths into a hash code with a fixed length of 160-bit. To achieve high-speed operation with small-area, arithmetic operation for step-operation is implemented by using a hybrid structure of 5:3 and 3:2 carry-save adders and carry-select adder. It computes a 160-bit hash code from a message block of 512 bits in 82 clock cycles, and has 312 Mbps throughput at 50 MHz@3.3-V clock frequency. The designed HAS-160 processor is verified by FPGA implementation, and it has 17,600 gates on a layout area of about $1\;mm^2$ using a 0.35-${\mu}m$ CMOS cell library.

Design of Invisible Watermarking for Biometric Image of Electronic ID Card (전자신분증용 바이오 영상을 위한 비인지 워터마킹 설계)

  • Shin, Yong-Nyuo;Lee, Yong-Jun;Kim, Won-Gyum
    • Journal of Korea Multimedia Society
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    • v.11 no.11
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    • pp.1555-1565
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    • 2008
  • Biometric information such as face and fingerprint information is highlighted in many security areas, including authentication, due to its uniqueness and convenience factors. However, if exploited maliciously, it can cause more serious damage than traditional security measures, like passwords. This paper reviews the watermarking method that is able to verify the integrity of this biometric information. The watermark to be inserted is the date of the biometric information acquisition. It is combined with 16-bit Cyclic Redundancy Checks prior to insertion. In particular, face and fingerprint images are saved in a specific compressed format. The proposed watermarking algorithm will be designed in such a way as to remain resilient against compression. The watermark inserted at the acquisition stage will be extracted at each storage and deployment stage, so that the integrity of the biometric information can be verified.

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