• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.33-43
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into a round transformation block, resulting that two consecutive round functions are simultaneously operated. For area-efficient and low-power implementation, the round transformation block is designed to share the hardware resources for encryption and decryption. An efficient on-the-fly key scheduler is devised to supports the three master-key lengths of 128-b/192-b/256-b, and it generates round keys in the first sub-pipeline stage of each round processing. The Verilog-HDL model of the cryptoprocessor was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}m$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Korean Journal of Plant Resources
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• v.31 no.6
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• pp.652-659
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• 2018

In this study, baicalin, as a marker substance of Scutellariae Radix, was quantitatively analyzed by a high performance liquid chromatography-photodiode array detector (HPLC-DAD). We identified wogonoside, baicalein, and wogonin in the Scutellariae Radix by a high performance liquid chromatography-electrospray ionization-mass spectrometer (HPLC-ESI-MS). The baicalin was separated on a Xterra C18 column ($5{\mu}m$, $4.6{\times}250mm$) using mobile phase consisting of 38% acetonitrile in 0.68% phosphoric acid. The baicalin spectrum in the Scutellariae Radix extracts was coincided by comparing with UV-visible spectrum (200-550 nm) of baicalin standard in the library. The amount of baicalin in Scutellariae Radix was 10.46%, which is higher than KFDA's guideline. The marker substances of Scutellariae Radix showed a strong base peak $[M]^+$ in the positive detection mode following as; baicalin (m/z; $271[MH^+-sugar]^+$, $447[M+H]^+$), wogonoside (m/z; $285[MH^+-sugar]^+$, $461[M+H]^+$), baicalein (m/z; $271\;[M+H]^+$), wogonin (m/z; $285[M+H]^+$). These results are consistent with the fragment pattern and molecular weight of standard components from literature.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.132-135
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.66-72
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• 2009

This paper proposes an efficient binary arithmetic encoder for CABAC which is used one of the entropy coding methods for H.264/AVC. The present binary arithmetic encoding algorithm requires huge complexity of operation and data dependency of each step, which is difficult to be operated in fast. Therefore, renormalization exploits 2-stage pipeline architecture for efficient process of operation, which reduces huge complexity of operation and data dependency. Context model updater is implemented by using a simple expression instead of transIdxMPS table and merging transIdxLPS and rangeTabLPS tables, which decreases hardware size. Arithmetic calculator consists of regular mode, bypass mode and termination mode for appearance probability of binary value. It can operate in maximum speed. The proposed binary arithmetic encoder has 7282 gate counts in 0.18um standard cell library. And input symbol per cycle is about 1.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.34-40
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• 2010

This paper proposes an efficient CABAC encoder to reduce syntax element storage in H.264/AVC entropy coding. In the proposed architecture, all blocks are designed in dedicated hardware, so it performs fast processing without programmable processors. Context modeler of CABAC encoder requires the neighbor block data. However it requires impractically huge memory size if the neighbor block data is directly stored without proper processing. Therefore, this paper proposes an effective method of storing the neighbor block data to decrease memory size. The proposed CABAC encoder has 35,463 gates in 0.18um standard cell library. It operates at maximum speed of 180MHz and its throughput is about 1 cycle per input symbol.

• Journal of Korean Physical Therapy Science
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• v.18 no.4
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• pp.31-46
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• 2011

The purpose of this survey was to give data and information about type and needs of Home Physical Therapy, Visiting Physical Therapy and School Physical Therapy for physical and nurse. The subjects were 154(99 physical therapists and 55 nurses) who were working at geriatric rehabilitation hospitals and children hospitals. The period of questionary collection was from the 15 of August to the 15th of September 2011. And data was analysis from 99 articles such as journals related to physical therapy, and searched with keyword 'home and visiting physical therapy' by web site and Korea National Assembly Library from 1991 to 2011. The data was analysis with percentage, mean, standard deviation and ANOVA by SPSS PC 12.0. The results were as follows; 1. The definition of 'Home Physical Therapy' has been community based on physical therapy service for the patient who had diagnosis by medical doctor, has been based on medical law. The definition of 'Visiting Physical Therapy' has been community based on physical therapy service at home for the patient who had diagnosis by medical doctor, for the national basic living security, and senior citizen over 65 years who lives alone, has been based on law for community health and law of long term health insurance. The definition of 'School Physical Therapy' has been school based on physical therapy service at school after class for the disabled children who are studying at school, has been based on special education law article 28. 2. As for the knowledge of the Home and Visiting and School Physical Therapy, both groups PT and nurse were 'I do not know'125(81.3%) of the difference the concept of 3 definitions, so it means to need education and information about the different concept of three physical therapy. As for the needs of home and visiting physical therapy, both groups of PT and Nurse were 'needs' 151(98.1%). Physical therapist showed of 'Needs' on visiting physical therapy 35(35.4%), home physical therapy 32(32.3%), and schole physical therapy 32(32.3%). Nurse showed of 'Needs' on home physical therapy 23(41.8%). visiting physical therapy 19(34.5%), school physical therapy 13(23.6%). Therefore it is necessary to have home and visiting physical therapy as for the elderly and disabled person. 3. As for the qualification of Home and Visiting physical therapist, both PT and nurse groups showed as follows; take post graduation education program for home and visiting therapy after became PT : home physical therapist 108(70.1%), visiting physical therapist 106(68.8%). So it means education center or university can be developed post graduation program for home and visiting physical therapist. 4. As for the 'Needs' of school physical therapy, both groups of PT and nurse showed as follows; 'Needs' 142(92.2%), 'Needs superviser education program' 148(96.1%), in PT group showed 'I will participate of education program' 92(92.9%). 5. As for the present states of research papers or report of home, visiting, and school physical therapy was as follows; the 103 papers for 8 fields about' the needs of home and visiting physical therapy' from 1991 to 2011, the 13 papers for 2 fields about school physical therapy from 2001 to 2011, so total papers were 114 articles.

• Journal of the Korean Association of Geographic Information Studies
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• v.19 no.3
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• pp.29-42
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• 2016

Remote sensing allows acquisition of information across a large area without contacting objects, and has thus been rapidly developed by application to different areas. Thus, with the development of remote sensing, satellites are able to rapidly advance in terms of their image resolution. As a result, satellites that use remote sensing have been applied to conduct research across many areas of the world. However, while research on remote sensing is being implemented across various areas, research on data processing is presently insufficient; that is, as satellite resources are further developed, data processing continues to lag behind. Accordingly, this paper discusses plans to maximize the performance of satellite image processing by utilizing the CUDA(Compute Unified Device Architecture) Library of NVIDIA, a parallel processing technique. The discussion in this paper proceeds as follows. First, standard KOMPSAT(Korea Multi-Purpose Satellite) images of various sizes are subdivided into five types. NDVI(Normalized Difference Vegetation Index) is implemented to the subdivided images. Next, ArcMap and the two techniques, each based on CPU or GPU, are used to implement NDVI. The histograms of each image are then compared after each implementation to analyze the different processing speeds when using CPU and GPU. The results indicate that both the CPU version and GPU version images are equal with the ArcMap images, and after the histogram comparison, the NDVI code was correctly implemented. In terms of the processing speed, GPU showed 5 times faster results than CPU. Accordingly, this research shows that a parallel processing technique using CUDA Library can enhance the data processing speed of satellites images, and that this data processing benefits from multiple advanced remote sensing techniques as compared to a simple pixel computation like NDVI.

• Journal of the Korean Society for information Management
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• v.26 no.2
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• pp.83-103
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• 2009

The Computer Interchange of Museum Information (CIMI), operating from 1990-2003, was charged with creating and introducing the international museum community to the concept of adopting metadata industry standards. The CIMI consortium exceeded its original mission by; creating a standards framework, profile, testbeds, important metadata publications, free downloadable metadata software and protocols, and providing instrumental guidance and support in development of new projects. However, CIMI's emphasis on the importance and utility of a standards-based approach and the necessity for implementing the CIMI Standards Framework is probably its most important achievement. During CIMI's tenure, museums reaped the benefits by learning how to apply the model and standards to meet their individual needs while not having to invent new ones or bear the cost of software development. Although CIMI operations ceased in 2003, its impacts on museum related metadata application and research were unprecedented in that it provided the standards prototype and foundations on which to build. This paper discusses what CIMI bequeathed to the next generation of museum metadata field developers and describes the anticipated realm of future projects and advancement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.79-84
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• 2006

This paper proposed a novel H.264 deblocking filter for low-power mobile multimedia SoCs. In H.264 deblocking filter, filtering can be skipped on some pixels when pixel value differences satisfy some specific conditions. Furthermore, whole filtering can be skipped when quantization parameter is less than 16. Based on these features, power consumption can be significantly reduced by shutting down deblocking filter partially or as a whole. The proposed deblocking filter can shut down partial or whole blocks with simple control circuits. Common hardware performs both horizontal filtering and vertical filtering. It was implemented in silicon chip using $0.35{\mu}m$ standard cell library technology. The gate count is about 20,000 gates. The maximum operation frequency is 108MHz. The maximum throughput is 30 frame/s with CCIR601 image format.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.35-42
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• 2007

The finite-field division can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field division takes much time to compute. In this paper, we propose a radix-4 systolic divider on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed divide, is mathematically developed and new counter structure is proposed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for YLSI design. Compared to the bit-parallel, bit-serial and digit-serial dividers, the proposed divider has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field divider using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.