• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.2562-2567
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• 2005

This paper suggests a new method discretization of nonlinear system using Taylor series expansion and zero-order hold assumption. This method is applied into the sampled-data representation of a nonlinear system with input time delay. Additionally, the delayed input is time varying and its amplitude is bounded. The maximum time-delayed input is assumed to be two sampling periods. Them mathematical expressions of the discretization method are presented and the ability of the algorithm is tested for some of the examples. And 'hybrid' discretization scheme that result from a combination of the ‘scaling and squaring' technique with the Taylor method are also proposed, especially under condition of very low sampling rates. The computer simulation proves the proposed algorithm discretized the nonlinear system with the variable time-delayed input accurately.

• Journal of Electrical Engineering and information Science
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• v.3 no.1
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• pp.73-79
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• 1998

In this paper, a new traffic sign detection algorithm.. and a symbol recognition algorithm are proposed. For traffic sign detection, a dominant color transform is introduced, which serves as a tool of highlighting a dominant primary color, while discarding the other two primary colors. For symbol recognition, the curvilinear shape distribution on a circle centered on the centroid of symbol, called a circular pattern vector, is used as a spatial feature of symbol. The circular pattern vector is invariant to scaling, translation, and rotation. As simulation results, the effectiveness of traffic sign detection and recognition algorithms are confirmed, and it is shown that group of circular patter vectors based on concentric circles is more effective than circular pattern vector of a single circle for a given equivalent number of elements of vectors.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.49 no.5
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• pp.205-211
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• 2000

This paper presents an optimal design method for fuzzy logic controller (FLC) of HVDC using an Adaptive Evolutionary Algorithm(AEA). We have proposed the AEA which uses a genetic algorithm (GA) and an evolution strategy (ES) in an adaptive manner in order to take merits of two different evolutionary algorithms. The AEA is used for tuning fuzzy membership functions and scaling constants. Simulation results show that disturbances are well damped and the dynamic performances of FLC have better responses than those of PD controller when AC system load changes suddenly.

• Electrical & Electronic Materials
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• v.7 no.2
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• pp.107-116
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• 1994

In the manufacturing of VLSI circuits, variations of device characteristics due to the slight differences in process parameters drastically aggravate the performances of fabricated devices. Therefore, it is very important to establish optimal process conditions in order to minimize deviations of device characteristics. In this paper, we used one-dimensional process simulator, SUPREM-II, and two dimensional device simulator, MINIMOS 4.0 in order to extract optimal process parameter which can minimize changes of the device characteristics caused by process parameter variation in the case of short channel nMOSFET and pMOSFET device. From this simulation, we have derived the dependence relations between process parameters and device characteristics. Here, we have suggested a method to extract process parameters from design trend curve(DTC) obtained by these dependence relations. And we have discussed short channel effects and device limitations by scaling down MOSFET dimensions.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.299-303
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• 1993

There can be two methods in control systems: one is to use a linear controller, the other is to use a nonlinear controller. The PID controller and the fuzzy controller can be said to belong the linear and the nonlinear controller respectively. In this paper, a new hybrid controller which is consist of the linear PID controller of which the gain is tuned and the nonlinear self tuning fuzzy controller is proposed. In the PID controller, an algorithm which parameterizes the proportional, the intergral, and the derivative gain as a single parameter is used to improve the performance of the PID controller. In the self tuning fuzzy controller, an algorithm which changes the shape of the triangle membership function and changes the scaling factor which is multiplied to the error and the error change. The evaluation of the performance of the suggested algorithm is carried on by the simulation for the Rhino XH-2 robot manipulator with 5 links revolute joints.

• 제어로봇시스템학회:학술대회논문집
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• 1989.10a
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• pp.649-652
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• 1989

In this paper we outline an approach for the collision-free trajectory planning of two robot arms which are modeled as connected line segments. A new approach to determine the collision between two robot arms and the boundary of the collision region in the coordination space is proposed. The coordination curve may then be chosen to avoid the collision region. For minimum time trajectory, time is assigned to this curve by dynamic time scaling under constraints such as maximum torque or maximum angular velocity of each actuator. A comparison of the proposed method and the graphical method of determining the collision region is also included. Finally, as an example, some simulation results for two SCARA type robots are presented.

• Journal of Mechanical Science and Technology
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• v.17 no.2
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• pp.187-196
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• 2003

In this paper, a new methodology of evolutionary computations - An Adaptive Evolutionary Algorithm (AEA) is proposed. AEA uses a genetic algorithm (GA) and an evolution strategy (ES) in an adaptive manner in order to take merits of two different evolutionary computations : global search capability of GA and local search capability of ES. In the reproduction procedure, the proportions of the population by GA and ES are adaptively modulated according to the fitness. AEA is used to. designing fuzzy logic controller (FLC) for a high-angle-of-attack flight system for a super-maneuverable version of F-18 aircraft. AEA is used to determine the membership functions and scaling factors of an FLC. The computer simulation results show that the FLC has met both robustness and performance requirements.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.530-537
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• 2013

An explicit surface potential calculation method of gate-all-around MOSFET (GAAMOSFET) devices which takes into account both interface trap charge and varying doping levels is presented. The results of the method are extensively verified by numerical simulation. Results from the model are used to find qualitative and quantitative effect of interface trap charge on subthreshold slope (SS) of GAAMOSFET devices. Further, design constraints of GAAMOSFET devices with emphasis on the effect of interface trap charge on device SS performance are investigated.

• 제어로봇시스템학회:학술대회논문집
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• 1995.10a
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• pp.127-130
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• 1995

Fuzzy controllers have proven to be powerful in controlling dynamic processes where mathematical models are unknown or intractable and ill-defined. The way of improving the performance of a fuzzy controller is based on making up rules, constructing membership functions, selecting a defuzzification method and adjusting input-output scaling factors. But there are many difficulties in tuning those to optimize a fuzzy controller. So, in this paper, we propose the look-up table based self-orgenizing fuzzy controller (LSOFC) which optimizes look-up values resulting from the above fuzzy processes. We use the plus-minus tuning method(PMTM), scanning the value through the processes of addition and subtraction. Simulation results demonstrate that the performance of LSOFC is far better than that of a non-tuning fuzzy controller.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.148-152
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• 2009

Recent CMOS technology scaling has seriously eroded the bit-line noise immunity of register files due to the consequent increase in active bit-line leakage currents. To restore its noise immunity while maintaining performance, we propose and evaluate a $256{\times}40$-bit register file incorporating dual-$V_t$ bit-lines with a boosted gate overdrive voltage in 65 nm bulk CMOS technology. Simulation results show that the proposed bootsrapping scheme lowers leakage current by a factor of 450 without its performance penalty.