• Journal of Power Electronics
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• 제19권2호
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• pp.413-430
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• 2019

This paper presents an optimum hybrid SVPWM technique for three-level voltage source inverters (VSIs). The proposed hybrid SVPWM technique aims to minimize total harmonic distortion (THD). A new parameter is introduced to incorporate the heterogeneous nature of switching sequences of SVPWM technique. The proposed hybrid SVPWM technique is implemented on a low-cost PIC microcontroller (PIC18F452) and verified experimentally with a 2 KVA three-phase three-level insulated gate bipolar transistor-based VSI. Optimum switching sequence results in the three-level inverter configuration are demonstrated. The proposed hybrid SVPWM technique improves the THD performance by 17.3% compared with the best available three-level SVPWM technique.

• 전력전자학회논문지
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• 제9권5호
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• pp.507-515
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• 2004

고속 스위칭 소자의 출현과 함께 높은 전압 상승률(dv/dt)은 PWM 인버터에 EMI 노이즈 및 축 전압 그리고 베어링 누설전류 등의 문제 등을 발생시키고 있다. 본 논문에서는 유도전동기 시스템에서의 새롭게 개발된 전도성 EMI 저감 SVPWM 기법의 응용에 대하여 기술한다. 새롭게 개발된 커먼모드 전압제거 SVPWM 기법은 인버터 제어에 있어서 영벡터 상태를 사용하지 않고 종래의 PWM 기법에 비하여 커먼모드 전압의 감소가 가능하다. 소프트웨어 접근에 의한 제안된 기법의 타당성은 시뮬레이션과 실험적 결과를 통하여 확인하였다.

• 전력전자학회논문지
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• 제7권1호
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• pp.1-10
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• 2002

본 논문에서는 2상 인버터용 공간전압벡터 PW 방식을 제안하였다. 제안된 2상 공간전압벡터 PWM 방식은 2상 유도전동기에 적용할 수 있다. 2상 공간전압벡터 방식을 사용하는 2상 인버터는 4개의 공간 전압벡터를 발생하나 영 전압 벡터는 만들 수 없다. 2상 인버터에서는 4개의 공간 전압벡터를 조정하여 기본 전압벡터를 실현한다. 또한, 2상 공간전압벡터방식에 의해 최적의 PWM 전압파형을 만들기 위한 대칭변조방식이 제안되었다. 제안된 2상 공간 전압벡터방식에 대한 타당성을 확인하기 위해 시뮬레이션과 실험이 실행되었다.

• Journal of Power Electronics
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• 제16권4호
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• pp.1336-1345
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• 2016

A modified space vector pulse width modulation (SVPWM) strategy based on vector space decomposition and its equivalent carrier-based PWM realization are proposed in this paper, which is suitable for six-phase asymmetrical dual stator induction machines (DSIMs). A DSIM is composed of two sets of symmetrical three-phase stator windings spatially shifted by 30 electrical degrees and a squirrel-cage type rotor. The proposed SVPWM technique can reduce torque ripples and suppress the harmonic currents flowing in the stator windings. Above all, the equivalent relationship between the proposed SVPWM technique and the carrier-based PWM technique has been demonstrated, which allows for easy implementation by a digital signal processor (DSP). Simulation and experimental results, carried out separately on a simulation system and a 3.0 kW DSIM prototype test bench, are presented and discussed.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2005년도 전력전자학술대회 논문집
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• pp.321-324
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• 2005

This paper describes the application of newly developed conducted EMI reduction technique of SVPWM in induction motor drive. The newly developed common mode voltage reduction SVPWM technique doesn't any zero-voltage vector states for inverter control. Hence it can restrict the common mode voltage better than conventional PWM technique. The proposed technique is verified through simulation and experimental results. And by applying vector-controled system, the proposed technique have superior ability of reducing EMI and equal control performance comparing conventional SVPWM technique.

• 전기전자학회논문지
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• 제24권1호
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• pp.19-24
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• 2020

본 논문은 FPGA의 언어 중 하나인 Verilog HDL을 사용한 100 kHz 스위칭의 3-레벨, 2-레벨 SVPWM 기법을 구현에 대한 것이다. 인버터에 주로 사용되는 IGBT소자의 경우 주로 20 kHz 근방에서 스위칭 주파수를 가진다. 최근 차세대 전력 반도체 소자의 연구 개발로 100 kHz 이상의 스위칭을 구현하여 전력변환기를 소형화하고, 고조파의 주입에 따른 여러 가지 새로운 알고리즘의 적용이 가능하게 되었다. IGBT를 이용하는 기존의 시스템에서는 DSP를 이용한 제어가 이루어지는 것이 통상적이나, 100 kHz 스위칭을 위한 제어기 구성으로는 FPGA를 이용한 제어기의 적용이 요구된다. 따라서 본 논문에서는 FPGA를 사용하여 2-레벨 인버터와 3-레벨 인버터에 적용되는 SVPWM의 이론과 FPGA 구현에 대하여 설명하고 SVPWM의 출력 파형을 통해 구현 성능을 확인한다. 한편, 본 논문에서는 3-레벨 인버터에서 SVPWM 구현 시 기존의 방식에서 반송파 2개를 사용하는 방법을 대신하여 반송파 1개만을 사용하는 기법으로 3-레벨 SVPWM을 구현한다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 추계학술대회 논문집
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• pp.25-28
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• 2002

In this paper, 2 phase modulated SRPP-PWM(Separately Random Pulse Position PWM) is proposed. This PWM technique is based on the 2 phase modulated SVPWM(Space Vector Pulse Width Modulation). In according to the theory of SVPWM, 2 phase modulated SVPWM uses two pulses, not three pulses as in 3 phase modulated SVPWM. In the proposed SRPP-PWM scheme, each of two phase pulses is located randomly in each switching interval. The experimental results show that the voltage and switching noise harmonics are spread to a wide band area. Also, the performance of the proposed 2 phase modulated SRPP-PWM and the conventional SVPWM are compared to each other In result, the speed response is nearly similar to each other from the viewpoint of the v/f constant control.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1999년도 전력전자학술대회 논문집
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• pp.399-402
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• 1999

The single sensor technique reconstructing phase currents from the dc-link current without phase current sensors in proposed. When the duration of active vector is too short for the snubber current to reduce, the dc-link current including the snubber current gives large detection error. The solution is presented by analyzing the snubber current and modifying the switching sequences. This scheme is simple, requires only one sampling a period and has good results for detecting the phase currents.

• Journal of Electrical Engineering and Technology
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• 제10권3호
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• pp.905-915
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• 2015

Two PWM techniques using space vector pulse-width modulation (SVPWM) are proposed for a two-phase permanent magnet synchronous motor (PMSM) driven by a two-phase eight-switch inverter. A two-phase motor with two symmetric stator windings is usually driven by a two-phase four-, six-, or eight-switch inverter. Compared with a four- and six-switch inverter, a two-phase eight-switch inverter can achieve larger power output. For two-phase motor drives, the SVPWM technique achieves more efficient DC bus voltage utilization and less harmonic distortion of the output voltage. For a two-phase PMSM fed by a two-phase eight-switch inverter under a normal SVPWM scheme, each of the eight PWM trigger signals for the inverter have to be changed twice in a cycle, causing a higher PWM frequency. Based on the normal SVPWM scheme, two effective SVPWM schemes are investigated in order to reduce the PWM frequency by rearranging four comparison values, while achieving the same function as the normal PWM scheme. A detailed explanation of the normal and two proposed SVPWM schemes is illustrated in the paper. The experimental results demonstrate that the proposed schemes achieve a better steady performance with lower switching losses compared with the normal scheme.

• Journal of Power Electronics
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• 제14권5호
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• pp.937-945
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• 2014

This paper presents an optimized space vector pulse-width modulation (OSVPWM) technique for a five-level cascaded H-bridge (CHB) inverter. The space vector diagram of the five-level CHB inverter is optimized by resolving it into inner and outer two-level space vector hexagons. Unlike conventional space vector topology, the proposed technique significantly reduces the involved computational time and efforts without compromising the performance of the five-level CHB inverter. A further optimized (FOSVPWM) technique is also presented in this paper, which significantly reduces the complexity and computational efforts. The developed techniques are verified through MATLAB/SIMULINK. Results are compared with sinusoidal pulse-width modulation (SPWM) to prove the validity of the proposed technique. The proposed simulation system is realized by using an XC3S400 field-programmable gate array from Xilinx, Inc. The experiment results are then presented for verification.