• Journal of Power Electronics
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• v.19 no.2
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• pp.413-430
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• 2019

This paper presents an optimum hybrid SVPWM technique for three-level voltage source inverters (VSIs). The proposed hybrid SVPWM technique aims to minimize total harmonic distortion (THD). A new parameter is introduced to incorporate the heterogeneous nature of switching sequences of SVPWM technique. The proposed hybrid SVPWM technique is implemented on a low-cost PIC microcontroller (PIC18F452) and verified experimentally with a 2 KVA three-phase three-level insulated gate bipolar transistor-based VSI. Optimum switching sequence results in the three-level inverter configuration are demonstrated. The proposed hybrid SVPWM technique improves the THD performance by 17.3% compared with the best available three-level SVPWM technique.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.5
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• pp.507-515
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• 2004

With the advent of fast power devices, the high dv/dt voltage produced by PWM inverts have been found to cause EMI noise, shaft voltage and bearing current. This paper describes the application of newly developed Conducted EMI reduction SVPWM technique in induction motor drives. The newly developed common mode voltage reduction SVPWM technique don't use any zero-vector states for inverter control, hence it can restrict the common mode voltage more than conventional PWM technique. The validity of the proposed technique by software approach is verified through simulation and experimental results.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.1
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• pp.1-10
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• 2002

In this paper the space voltage vector pulsewidth modulation(SVPWM) technique for two-phase inverter is proposed. The two-phase SVPWM technique is applicable to two-phase induction motor drives. The two-phase inverter using two-phase SVPWM technique cannot generate zero voltage vectors, but four space vectors. A reference voltage vector in the square locus is realized by adjusting four space vectors. The switching sequence "two-phase symmetrical modulation" used in two-phase SVPWM is proposed. Practical verification of theoretical predictions is presented to conform the capabilities of the new technique.technique.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1336-1345
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• 2016

A modified space vector pulse width modulation (SVPWM) strategy based on vector space decomposition and its equivalent carrier-based PWM realization are proposed in this paper, which is suitable for six-phase asymmetrical dual stator induction machines (DSIMs). A DSIM is composed of two sets of symmetrical three-phase stator windings spatially shifted by 30 electrical degrees and a squirrel-cage type rotor. The proposed SVPWM technique can reduce torque ripples and suppress the harmonic currents flowing in the stator windings. Above all, the equivalent relationship between the proposed SVPWM technique and the carrier-based PWM technique has been demonstrated, which allows for easy implementation by a digital signal processor (DSP). Simulation and experimental results, carried out separately on a simulation system and a 3.0 kW DSIM prototype test bench, are presented and discussed.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.321-324
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• 2005

This paper describes the application of newly developed conducted EMI reduction technique of SVPWM in induction motor drive. The newly developed common mode voltage reduction SVPWM technique doesn't any zero-voltage vector states for inverter control. Hence it can restrict the common mode voltage better than conventional PWM technique. The proposed technique is verified through simulation and experimental results. And by applying vector-controled system, the proposed technique have superior ability of reducing EMI and equal control performance comparing conventional SVPWM technique.

• Journal of IKEEE
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• v.24 no.1
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• pp.19-24
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• 2020

This paper presents a 3-level, 2-level SVPWM technique with 100 kHz switching using Verilog HDL, one of the languages of FPGA. In the case of IGBT devices mainly used in inverters, they have a switching frequency around 20kHz. Recent research and development of next-generation power semiconductor devices such as GAN has enabled switching of more than 100kHz, which can miniaturize power converters, and apply various new algorithms due to the injection of harmonics. In the existing system using the IGBT, the control using the DSP is common, but the controller configuration for 100 kHz switching requires the use of FPGA. Therefore, this paper explains the theory and implementation of SVPWM applied to two-level and three-level inverters using FPGAs and verifies the performance through the output waveform. In addition, this paper implements 3-level SVPWM by using only one carrier instead of using two carriers in the conventional method.

• Proceedings of the KIPE Conference
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• 2002.11a
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• pp.25-28
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• 2002

In this paper, 2 phase modulated SRPP-PWM(Separately Random Pulse Position PWM) is proposed. This PWM technique is based on the 2 phase modulated SVPWM(Space Vector Pulse Width Modulation). In according to the theory of SVPWM, 2 phase modulated SVPWM uses two pulses, not three pulses as in 3 phase modulated SVPWM. In the proposed SRPP-PWM scheme, each of two phase pulses is located randomly in each switching interval. The experimental results show that the voltage and switching noise harmonics are spread to a wide band area. Also, the performance of the proposed 2 phase modulated SRPP-PWM and the conventional SVPWM are compared to each other In result, the speed response is nearly similar to each other from the viewpoint of the v/f constant control.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.399-402
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• 1999

The single sensor technique reconstructing phase currents from the dc-link current without phase current sensors in proposed. When the duration of active vector is too short for the snubber current to reduce, the dc-link current including the snubber current gives large detection error. The solution is presented by analyzing the snubber current and modifying the switching sequences. This scheme is simple, requires only one sampling a period and has good results for detecting the phase currents.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.905-915
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• 2015

Two PWM techniques using space vector pulse-width modulation (SVPWM) are proposed for a two-phase permanent magnet synchronous motor (PMSM) driven by a two-phase eight-switch inverter. A two-phase motor with two symmetric stator windings is usually driven by a two-phase four-, six-, or eight-switch inverter. Compared with a four- and six-switch inverter, a two-phase eight-switch inverter can achieve larger power output. For two-phase motor drives, the SVPWM technique achieves more efficient DC bus voltage utilization and less harmonic distortion of the output voltage. For a two-phase PMSM fed by a two-phase eight-switch inverter under a normal SVPWM scheme, each of the eight PWM trigger signals for the inverter have to be changed twice in a cycle, causing a higher PWM frequency. Based on the normal SVPWM scheme, two effective SVPWM schemes are investigated in order to reduce the PWM frequency by rearranging four comparison values, while achieving the same function as the normal PWM scheme. A detailed explanation of the normal and two proposed SVPWM schemes is illustrated in the paper. The experimental results demonstrate that the proposed schemes achieve a better steady performance with lower switching losses compared with the normal scheme.

• Journal of Power Electronics
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• v.14 no.5
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• pp.937-945
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• 2014

This paper presents an optimized space vector pulse-width modulation (OSVPWM) technique for a five-level cascaded H-bridge (CHB) inverter. The space vector diagram of the five-level CHB inverter is optimized by resolving it into inner and outer two-level space vector hexagons. Unlike conventional space vector topology, the proposed technique significantly reduces the involved computational time and efforts without compromising the performance of the five-level CHB inverter. A further optimized (FOSVPWM) technique is also presented in this paper, which significantly reduces the complexity and computational efforts. The developed techniques are verified through MATLAB/SIMULINK. Results are compared with sinusoidal pulse-width modulation (SPWM) to prove the validity of the proposed technique. The proposed simulation system is realized by using an XC3S400 field-programmable gate array from Xilinx, Inc. The experiment results are then presented for verification.