• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.1
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• pp.1-5
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• 2001

STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.

• STI Policy Review
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• v.4 no.2
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• pp.19-40
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• 2013

The Association of Southeast Asian Nations (ASEAN) achieved relatively rapid economic growth over the past decade. Sustainable growth among member states, however, is put into question due to macroeconomic challenges, political risk, and vulnerability to external shocks. Developed countries, in contrast, have turned into less labor-intensive technologies to further expand their economies. In this paper, we review the science, technology, and innovation (STI) policies and statuses of the scientific and technological capabilities of the ASEAN member countries. Empirical results based on STI indicators (R&D spending, publications, patents, and knowledge economy indices) reveal considerable variation between the science and technology (S&T) competence and effectiveness of STI policies of ASEAN members. We have categorized nations into clusters according their situations in their S&T productivity. Under the Korean Innovation Model, Cambodia, Laos, Myanmar, and Brunei are classified as being in the institutional-building stage, while Malaysia, Thailand, Indonesia, the Philippines, and Vietnam in the catch up stage, and Singapore in the post-catch up stage. Finally, policy prescriptions on how to enhance the S&T capabilities of the developing ASEAN countries, based on the South Korea development experience, are presented.

• STI Policy Review
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• v.1 no.3
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• pp.1-15
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• 2010

This paper makes the case that a new policy strategy to enhance a global green recovery is needed urgently. The new strategy requires two essential elements. First, G20 economies should follow the lead of South Korea and China and turn their green stimulus investments into a serious long-term commitment, and to support these investments, they should adopt environmental pricing policies and instigate pricing and regulatory reforms to reduce carbon dependency. Second, the G20 also needs to target and coordinate assistance to developing economies in science, technology and innovation (STI) for clean energy. Such assistance is essential to help developing economies to overcome the skills, technological and capital gap that they face in clean energy technologies over the long term. Reform of the Clean Development Mechanism (CDM) is also necessary to establish a long-term global price signal for carbon, and to increase the coverage of developing economies, the sectors and technologies and the overall financing of clean energy projects. Formulating such a policy strategy should appeal to both the Asian-Pacific and Western economies comprising the G20, and by working together to formulate such a strategy, the G20 could lead the way toward a new era of global economic management and STI cooperation in clean energy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.45-51
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• 2004

We have proposed a new shallow trench isolation (STI) process using flowable oxide (F-oxide) chemical vapor deposition (CVD) for DRAM application and it was successfully developed. The combination of F-oxide CVD and HDP CVD is thought to be the superior STI gap-filling process for next generation DRAM fabrication because F-oxide not only improves STI gap-filling capability, but also the reduced local stress by F-oxide in narrow trenches leads to decrease in junction leakage and gate induced drain leakage (GIDL) current. Finally, this process increased data retention time of DRAM compared to HDP STI. However, a serious failure occurred by symphonizing its structural dependency of deposited thickness with poor resistance against HF chemicals. It could be suppressed by reducing the flow time during F-oxide deposition. It was investigated collectively in terms of device yield. In conclusion, the combination of F-oxide and HDP oxide is the very promising technology for STI gap filling process of sub-100nm DRAM technology.

• Journal of Science and Technology Studies
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• v.11 no.1
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• pp.61-88
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• 2011

This paper presents theoretical discussions on socio-techical system transition, by shedding light on the STS context. With a rising attention paid by STI policy researchers, the socio-technical system perspective seems particularly promising in applying to the pursuit for the sustainable development. The normative strand in STI policy research has been strongly influenced by the STS tradition that emphasizes active and participatory roles not only of academian but also of science and technology. Throughout reviewing the development of the socio-technical system perspective, its theoretical components of environment, drivers and dynamics are discussed, often being linked to older perspectives. STI policy involves in socio-technical transition in a manner of transition management and governance, which is the final part of this paper.

• Transactions on Electrical and Electronic Materials
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• v.3 no.3
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• pp.18-20
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• 2002

In sub-l/4 ${\mu}{\textrm}{m}$ NMOSFET with STI (Shallow Trench Isolation), the anomalous hump phenomenon of subthreshold region, due to capped p-TEOS/SiN induced defect, is reported. The hump effect was significantly observed as channel length is reduced, which is completely different from previous reports. Channel boron dopant redistribution due to the defect should be considered to improve hump characteristics besides considerations of STI comer and recess. 130

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.10b
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• pp.443-444
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• 2002

The uniformity of field oxide is critical to isolation property of device in STI, so the control of field oxide thickness in STI-CMP becomes enormously important. The loss of field oxide in shallow trench isolation comes mainly from dishing and erosion in STI-CMP. In this paper, the effect of slurries on the dishing was investigated with both blanket and patterned wafers were selected to measure the removal rate, selectivity and dishing amount. Dishing was a strong function of pattern spacing and types of slurries. Dishing was significantly decreased with decreasing pattern spacing for both slurries. Significantly lower dishing with ceria based slurry than with silica based slurry were achieved when narrow pattern spacing were used. Possible dishing mechanism with two different slurries were discussed based on the observed experimental results.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.05a
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• pp.272-278
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• 2002

Recently, STI(Shallow Trench Isolation) process has attracted attention for high density of semiconductor device as a essential isolation technology. In this paper, the effect of pattern density, trench width and selectivity of slurry on dishing in STI CMP process was investigated by using specially designed isolation pattern. As trench width increased, the dishing tends to increase. At $20{\mu}m$ pattern size, the dishing was decreased with increasing pattern density Low selectivity slurry shows less dishing at over $160{\mu}m$ trench width, whereas high selectivity slurry shows less dishing at below $160{\mu}m$ trench width.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.35-38
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• 2000

In this study, the rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.l8um semiconductor device. Through reverse moat pattern process, reduced moat density at high moat density, STI CMP process with low selectivity could be to fit polish uniformity between low moat density and high moat density. Because this reason, in-situ motor current end point detection method is not fit to the current EPD technology with the reverse moat pattern. But we use HSS without reverse moat pattern on STI CMP and take end point current sensing signal.[1] To analyze sensing signal and test extracted signal, we can to adjust wafer difference within $110{\AA}$.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.64-64
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• 2003

고집적화된 시스템 LSI 반도체 소자 제조 공정에서 소자의 고속화 및 고성능화에 따른 배선층수의 증가와 배선 패턴 미세화에 대한 요구가 갈수록 높아져, 광역평탄화가 가능한 STI CMP(Shallow Trench Isolation Chemical-Mechanical-Polishing)공정의 중요성이 더해가고 있다. 이러한 STI CMP 공정에서 세리아 슬러리에 첨가되는 계면활성제의 농도에 따라 산화막과 질화막 사이의 연마 선택비를 제어하는 것이 필수적 과제로 등장하고 있다. 일반적인 CMP 공정에서 압력 증가에 따른 연마 제거량이 Prestonian 거동을 나타내는 반면, 연마 입자의 크기를 변화시켜 계면활성제의 농도를 달리 하였을 경우, 압력 변화에 따라 Non-Prestonian 거동이 나타나는 것을 고찰할 수 있었다. 따라서 본 연구에서는 세리아 슬러리 내에 첨가되는 계면활성 제의 농도와 연마입자의 크기를 달리한 후, 압력을 변화시킴으로 나타나는 non-Prestonian 거동에 미치는 영향에 대하여 연구하였다.