• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.22-28
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• 2015

This paper proposes column-parallel three step Single Slope Analog-to-Digital Converter (SS-ADC) for high frame rate VGA CMOS Image Sensors (CISs). The proposed three step SS-ADC improves the sampling rate while maintaining the architecture of the conventional SS-ADC for high frame rate CIS. The sampling rate of the three-step ADC is increased by a factor of 39 compared with the conventional SS-ADC. The proposed three-step SS-ADC has a 12-bit resolution and 200 kS/s at 25 MHz clock frequency. The VGA CIS using three step SS-ADC has the maximum frame rate of 200 frames/s. The total power consumption is 76 mW with 3.3 V supply voltage without ramp generator buffer. A prototype chip was fabricated in a $0.13{\mu}m$ CMOS process.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.465-471
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• 2023

This paper proposes a comparator structure that improves the noise and output delay of a single-slope ADC(SS-ADC) used in CMOS Image Sensor (CIS). To improve the noise and delay characteristics of the output, a comparator structure using the miller effect is designed by inserting a capacitor between the output node of the first stage and the output node of the second stage of the comparator. The proposed comparator structure improves the noise, delay of the output, and layout area by using a small capacitor. The CDS counter used in the single slop ADC is designed using a T-filp flop and bitwise inversion circuit, which improves power consumption and speed. The single-slope ADC also performs dual CDS, which combines analog correlated double sampling (CDS) and digital CDS. By performing dual CDS, image quality is improved by reducing fixed pattern noise (FPN), reset noise, and ADC error. The single-slope ADC with the proposed comparator structure is designed in a 0.18-㎛ CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.246-251
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• 2014

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA ($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.20-27
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• 2011

A CMOS Image Sensor(CIS) mounted on mobile appliances always needs a low power consumption because of the battery life cycle. In this paper, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination, a low power single slope A/D converter with a novel comparator, and etc. Based on 0.13um CMOS process, the chip satisfies QVGA resolution($320{\times}240$ pixels) whose pitch is 2.25um and whose structure is 4-Tr active pixel sensor. From the experimental results, the ADC in the middle of CIS has a 10-b resolution, the operating speed of CIS is 16 frame/s, and the power dissipation is 25mW at 3.3V(Analog)/1.8V(Digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption is reduced approximately by 22% in sleep mode, 20% in operating mode.

• Journal of radiological science and technology
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• v.44 no.1
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• pp.25-30
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• 2021

The purpose was to reduce the distortion of the image that occurs in the temporal bone area due to the very strong differences in susceptibility. A new SS-TSE technique was applied when examining the diffusion-weighted image of the temporal bone, where the auditory and facial nerves to be imaged were very thin and were adjacent to the cranial base including bone and air. This study was conducted from March 2020 to August of the same year, targeting 32 subjects who underwent the diffusion-weighted imaging of the temporal bone. To compare the distortion, existing SS-EPI technique and the new SS-TSE technique were both applied on the temporal bone area. As a result of the study, applying the new SS-TSE technique appeared to lower the distortion of images by 87.44, 46.13 and 42.35 % on the b-value 0, 800 and the ADC images, respectively. In conclusion, when using the new SS-TSE technique on the temporal bone DWI, distortion can be reduced, and thus images with high diagnostic value can be obtained.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.110-119
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• 2017

This paper describes a CMOS image sensor (CIS) with dual correlated double sampling (CDS) and column-parallel analog-to-digital converter (ADC) and its measurement method using a field-programmable gate array (FPGA) integrated module. The CIS is composed of a $320{\times}240$ pixel array with $3.2{\mu}m{\times}3.2{\mu}m$ pixels and column-parallel 10-bit single-slope ADCs. It is fabricated in a $0.11-{\mu}m$ CIS process, and consumes 49.2 mW from 1.5 V and 3.3 V power supplies while operating at 6.25 MHz. The measured dynamic range is 53.72 dB, and the total and column fixed pattern noise in a dark condition are 0.10% and 0.029%. The maximum integral nonlinearity and the differential nonlinearity of the ADC are +1.15 / -1.74 LSB and +0.63 / -0.56 LSB, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12C
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• pp.1131-1137
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• 2009

In this paper, a resource management technique for digital duplexing (DD) systems using orthogonal frequency division multiple access (OFDMA) is proposed. The proposed technique can reduce the dynamic range of the signal received at the subscriber station (SS) and minimize the effects of inter-symbol interference (ISI) and inter-carrier interference (ICI) due to the time difference of arrival (TDoA) without using a cyclic suffix. It is shown by computer simulation that the proposed technique can reduce the number of bits for an analog-to-digital converter (ADC) and increase the signal-to-interference and noise ratio (SINR) significantly.

• Korean Journal of Animal Reproduction
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• v.25 no.4
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• pp.295-304
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• 2001

Characterization of quantitative trait loci (QTL) was investigated in the experimental crosses between Berkshire and Yorkshire breed. A total of 525 F$_2$ progenies from 65 matting of F$_1$ Parents were produced. Phenotypic measurements included average daily gain (ADG), average back fat thickness (ABF), and loin eye area (LEA). To identify the presence of QTL for reproductive performance, birth weight (BWT) and body weight at 16 days (16DAY) were included as indirect trait. QTL segregation was deduced using 8 markers assigned to chromosome 2 (SSC2). Quantitative trait locus analyses were performed using interval mapping by regression under line-cross model. Presence of imprinting was tested under the statistical model that separated the expression of paternally and maternally inherited alleles. To set the evidence of QTL presence, significance thresholds were derived by permutation following statistical tests, respectively. Genome scan revealed significant evidence for three quantitative trait loci (QTL) affecting growth and body compositions, of which two were identified to be QTL with imprinting expression mode near the ICF II gene region. For average back fat thickness (ABF), a paternally expressed QTL was found on chromosome 2 (SSC2). A paternally expressed QTL affecting loin eye area (LEA) was found in the region of SSC2 where evidence of imprinted QTL was found for average back fat thickness (ABF). For average daily gain (ADG), QTL expressed with Mendelian mode was found on chromosome 2 (SS2). Also, QTL affecting average daily gain (ADC), was identified to be expressed with Mendelian express mode.