• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.1
• /
• pp.83-91
• /
• 2000

This paper presents a new technique to reduce a large interconnect circuit with tens of thousands of elements into the one that is small enough to be analyzed by circuit simulators such as SPICE. This technique takes a fundamentally different approach form the conventional methods based on the interconnect circuit structure analysis and several rules based on the Elmore time constant. The time moments are computed form the circuit consisting of the interconnect circuit and the CMOS gate driver model computed by the AWE technique. Then, the equivalent RC circuit is synthesized from those moments. The characteristics of the driving CMOS gate can be reflected with the high degree of accuracy and the size of the compressed circuit is determined by the number of output nodes regardless of the size of the original interconnect circuits. This technique has been implemented in C language, applied to several interconnect circuits driven by a 0.5${\mu}m$ CMOS gate and the equivalent RC circuits with more than 99% reduction ratio and accuracy with 1 ~ 10% error in therms of propagation delays were obtained.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.4 no.4
• /
• pp.346-351
• /
• 2003

In spite of the size and complexity of software becomes large and complicated, the demand of rapid development, cost reduction, good productivity and good quality software is increasing in these days. Many methods were proposed for efficient software development such as various Case tools. Metrics, Process improvement model (CMM, SPICE, ISO9000) and etc. However, most of them we useful to manage the whole projects rather than an individual programming. In this paper, we introduced a system for quality assessment and complexity metrics for Java programs to assess the individual programmer's quality rather than team's quality. This system shows not only the metrics value for quality assessment but also the source code and the soucture of classes simultaneously.

• Journal of Biomedical Engineering Research
• /
• v.29 no.5
• /
• pp.392-399
• /
• 2008

Thin-film transistor (TFT) arrays for an x-ray detector require quite different design concept from that of the conventional active-matrix liquid crystal devices (AM-LCDs). In this paper anew design of TFT array which uses only SiNx for passivation layer is described to meet the detector performance and the product availability simultaneously. For the purpose of optimizing the design parameters of the TFT array, a Spice simulation was performed. As a result, some parameters, such as the TFT width, the data line capacitance, and the storage capacitance, were able to be fixed. The other parameters were decided within a permissible range of the TFT process especially the photolithography process and the wet etch process. Then we adapted the TFT array which had been produced by the proposed design to our prototype model (FDXD-1417 and evaluated it clinically by comparing with a commercial model (EPEX, Hologic, Beford, USA). The results say that our prototype model is slightly better than EPEX system in chest PA images. So we can prove the technical usefulness and the commercial values of the proposed TFT design.

• Smart Structures and Systems
• /
• v.14 no.2
• /
• pp.247-266
• /
• 2014

Conventional cantilevered piezoelectric energy harvesters (PEHs) are usually fabricated with continuous electrode configuration (CEC), which suffers from the electrical cancellation at higher vibration modes. Though previous research pointed out that the segmented electrode configuration (SEC) can address this issue, a comprehensive evaluation of the PEH with SEC has yet been reported. With the consideration of delivering power to a common load, the AC outputs from all segmented electrode pairs should be rectified to DC outputs separately. In such case, theoretical formulation for power estimation becomes challenging. This paper proposes a method based on equivalent circuit model (ECM) and circuit simulation to evaluate the performance of the PEH with SEC. First, the parameters of the multi-mode ECM are identified from theoretical analysis. The ECM is then established in SPICE software and validated by the theoretical model and finite element method (FEM) with resistive loads. Subsequently, the optimal performances with SEC and CEC are compared considering the practical DC interface circuit. A comprehensive evaluation of the advantageous performance with SEC is provided for the first time. The results demonstrate the feasibility of using SEC as a simple and effective means to improve the performance of a cantilevered PEH at a higher mode.

• Journal of the Semiconductor & Display Technology
• /
• v.22 no.4
• /
• pp.179-184
• /
• 2023

We propose the modeling methodology of CMOS inverter made of LTPO TFT using a machine learning. LTPO can achieve advantages of LTPS TFT with high electron mobility as a driving TFT and IGZO TFT with low off-current as a switching TFT. However, since the unified model of both LTPS and IGZO TFTs is still lacking, it is necessary to develop a SPICE-compatible compact model to simulate the LTPO current-voltage characteristics. In this work, a generic framework for combining the existing formula of I-V characteristics with artificial neural network is presented. The weight and bias values of ANN for LTPS and IGZO TFTs is obtained and implemented into PSPICE circuit simulator to predict CMOS inverter. This methodology enables efficient modeling for predicting LTPO TFT circuit characteristics.

• Journal of Biomedical Engineering Research
• /
• v.16 no.4
• /
• pp.415-424
• /
• 1995

Combined models, specified by two or more modeling formalisms, can represent a wide variety of complex systems. This paper describes a methodology for the development of combined models in two model types of discrete event and continuous process. The methodology is based on transformation of continuous state space into discrete one to homomorphically represent dynamics of continuous processes in discrete events. This paper proposes a formal structure which can combine model of the DES and the CS within a framework. The structure employs the DEVS formalism for the DES models and differential or polynomial equations for the CS models. To employ the proposed structure to specify a DEVS/CS combined model, a modeler needs to take the following steps. First, a modeler should identify events in the CS and transform the states of the CS into the DES. Second, a modular employs the formalism to specify the system as the DES. Finally, a moduler developes sub-models for the CS and continguos states of the DES and establishs one-to-one correspondence between the sub-models and such states. The proposed formal structre has been applied to develop a DEVS/CS combined model for the human cardiovascular system. For this, the cardiac cycle is partitioned into a set of phases based on events identified through observation. For each phase, a CS model has been developed and associated with the phase. To validate the DEVS/CS combined model developed, then simulate the model in the DEVSIM + + environment, which is a model simulation results with the results obtained from the CS model simulation using SPICE. The comparison shows that the DEVS/CS combined model adequately represents dynamics of the human heart system at each phase of cardiac cycle.

• Proceedings of the IEEK Conference
• /
• 2004.06b
• /
• pp.447-450
• /
• 2004

The modeling circuit becomes more important in developing various magnetic devices regarding the fact that the competitive architecture and circuitry should be developed simultaneously. In this paper, we introduce a modeling circuit for hysteresis characteristic of a magnetic device, which is a major characteristic in the spin dependent magnetic material. This transistor-level model is conspicuous in that it can be usefully embodied in real circuits rather than conventional SPICE models are only for simulations.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2006.05a
• /
• pp.235-238
• /
• 2006

최근 많은 기업들은 효과적인 소프트웨어 프로세스 개선을 위해 SPICE와 CMMI 프로세스 심사 표준을 도입하려는 노력을 하고 있다. 이러한 표준을 통해 효과적인 개선하기 위해서는 개선점과 위험을 식별하고 이들 이슈들을 소프트웨어 개발환경(software development environment)에 적용시켜서 조직의 비젼(organization vision)에 대응한 작업성능(work performance)를 높여야한다. 지속적인 개선을 필요로 하는 조직은 현재의 작업성능을 측정하고 이를 개선하기 위한 개선점을 찾아내는 능력과 경험을 축적하여 체계적으로 관리하는 것이 중요하다. 하지만 기존의 SPI 모델들은 무엇을 수행해야 하는지에 대한 지침은 제공하고 있지만, 정량적인 작업성능 측정 및 특정 환경의 소프트웨어 개발 조직의 SPI를 위해 필요한 구체적인 지침을 제시하고 있지는 않다. 따라서, 본 논문에서는 이러한 조직의 작업성능 측정 및 조직의 개선경험을 축적하여 프로세스를 개선전략에 반영하여 조직의 비젼에 최적한 전략을 제공해주는 OTEM(Opportunity Tree Enterprise Model)을 제안한다.

• Journal of Electrical Engineering and Technology
• /
• v.4 no.3
• /
• pp.396-400
• /
• 2009

In this paper, electromagnetic topology (EMT) was used to analyze the electromagnetic compatibility (EMC) of RF circuits including passive and active components. It is difficult to obtain usable results for problems relating to electromagnetic coupling in complex systems when using conventional numerical or experimental methods. Thus it is necessary to find a new methodology for analyzing EMC problems in complicated electromagnetic environments. In order to consider the nonlinear characteristics of active components, a SPICE diode model was used. A power detector circuit and the receiver circuit of a radio control (RC) car were analyzed and experimented in order to verify the validity of this method.

• Proceedings of the KIEE Conference
• /
• 2006.10d
• /
• pp.244-246
• /
• 2006

Softwares in railway system are being used in the area of railway control system, directly associated to safety. Because the instinct characteristic of Software is uncertainty, Software development without safety insurance is very hazardous situation. In order to derive safety certification process in the railway system, certification and approval processes in the nuclear, aviation, and military area are studied. Software quality should be improved by two aspects : one is product aspect, another is process aspect. GS(Good Software) and ES(Excellent Software) certification can be exemplified in a product aspect approach. In those process certification, CMMI (Capability Maturity Model Integration) or SPICE (Software Process Improvement and Capability dEtermination : ISO/IEC15504) is being used as models for assessing process maturity of organization. Following the studies, safety management procedure in the railway system is suggested.