• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.10
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• pp.815-820
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• 2012

We introduce two-dimensional soft output Viterbi algorithm (2D SOVA) and iterative 2D SOVA for holographic data storage. Since the holographic data storage is 2D intersymbol interference (ISI) channel, the 2D detection schemes have good performance at holographic data storage. The 2D SOVA and iterative 2D SOVA are 2D detection schemes. We introduce and compare the two 2D detection schemes. The 2D SOVA is approximately 2 dB better than one-dimensional (1D) detection scheme, and iterative 2D SOVA is approximately 1 dB better than the 2D SOVA. In contrast, the iterative 2D SOVA is approximately twice complex higher than 2D SOVA, and 2D SOVA is approximately twice complex higher than 1D detection scheme.

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.257-265
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• 2000

Turbo Code decoder is an iterate decoding technology, which extracts extrinsic information from the bit to be decoded by calculating both forward and backward metrics in each decoding step, and uses the information to the next decoding step. Viterbi decoder, which is for a convolutional code, runs continuous mode, while Turbo Code decoder runs by block unit. There are algorithms used in a decoder : which are MAP(maximum a posteriori) algorithm requiring very complicated calculation and SOVA(soft output Viterbi algorithm) using Viterbi algorithm suggested by Hagenauer, and it is known that the decoding performance of MAP is better. The result of this make experimentation shows that the performance of SOVA, which has half complex algorithm compare to MAP, is almost same as the performance of MAP when the SOVA decoding performance is supplemented with Robust equalization techniques.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3157-3159
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• 2000

Soft Output Viterbi Algorithm is modification of Viterbi algorithm to deliver not only the decoded codewords but also a posteriori probability for each bit. This paper presents SOVA decoder which can be used for component decoder of turbo decoder. We used two-step SMU architectures combined with systolic array traceback methods to reduce the complexity of the design. We followed the specification of CDMA2000 system for SOVA decoder design.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.3
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• pp.19-28
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• 1998

This paper is concerned with the implementation of the equalization technique in a DCS 1800 system employing the soft-decision output Viterbi algorithm (SOVA), which makes the hardware complexity comparable to the hard decision MLSE and gives reliable performance. Also, the channel estimation technique with enhances the perfdormance of the soft-decision output equalizer is proposed, and the Viterbi decoder which operates effectively with the soft-decision output of the qualizer is implemented using the Very High Speed ICs Hardware Description Language (VHDL). From the simulation results, it is shown that the implemented Viterbi decoder operates effectively and the SOVA outperforms the hard-decision MLSE in terms of the frame erasure rate (FER) and bit error rate (BER).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.438-443
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• 2008

The efficient method to implement the Max-Log-MAP algorithm is proposed by modifying the conventional algorithm. It is called a parallel soft output Viterbi algorithm (SOVA) and the rigorous proof is given for the equivalence between the Max-Log-MAP algorithm and the parallel SOVA. The parallel SOVA is compared with the conventional algorithms and we show that it is an efficient algorithm implementing the modified SOVA in parallel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11C
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• pp.896-900
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• 2010

We investigate the bit error rate against signal-to-noise ratio performance corresponding to track mis-registration for patterned media storage. The patterned media channels with and without soft underlayer are implemented, and we simulate using one-dimensional Viterbi detector and two-dimensional soft output Viterbi detector (SOVA) when the track mis-registration is 0% (on-track), 10%, 20%, 30%, and 40%. While the BER performance degrades approximate 0.3 ~ 0.5 dB at 10% track mis-registration, it degrades severe over 10% track mis-registration.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.14-23
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• 2002

Two implementation methods for SOVA (Soft Output Viterbi Algorithm)of Turbo decoder are applied and verfied. The first method is the combination of a trace back (TB) logic for the survivor state and a double trace back logic for the weight value in two-step SOVA. This architecure of two-setp SOVA decoder allows important savings in area and high-speed processing compared with that of one-step SOVA decoding using register exchange (RE) or trace-back (TB) method. Second method is adjusting the reliability value with a scaling factor between 0.25 and 0.33 in order to compensate for the distortion for a rate 1/3 and 8-state SOVA decoder with a 256-bit frame size. The proposed schemes contributed to higher SNR performance by 2dB at the BER 10E-4 than that of SOVA decoder without a scaling factor. In order to verify the suggested schemes, the SOVA decoder is testd using Xillinx XCV 1000E FPGA, which runs at 33.6MHz of the maximum speed with 845 latencies and it features 175K gates in the case of 256-bit frame size.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1045-1051
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• 2003

The SOVA, which produces the soft decision value, can be used as a sub-optimum solution for concatenated codes such as turbo codes, since it is computationally efficient compared with the optimum MAP algorithm. In this paper, we propose an efficient implementation of the SOVA used for decoding turbo codes, by reducing the number of calculations for soft decision values and trace-back operations. In order to utilize the memory efficiently, the whole block of turbo codes is divided into several sub-blocks in the proposed algorithm. It is demonstrated that the proposed algorithm requires less computation than the conventional algorithm, while providing the same overall performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12A
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• pp.1983-1989
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• 2001

A new two-step soft output Viterbi algorithm (SOVA) for turbo decoder is proposed and analyzed in 7his paper. Due to the algebraic structure of the proposed algorithm, slate and branch metrics can be obtained wish parallel processing using matrix arithmetic. As a result, the number of multiplications to calculate state metrics of each stage and total memory size can be decreased tremendously. Therefore, it can be expected that the proposed algebraic two-step SOVA is suitable for applications in which low computational complexity and memory size are essential.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.384-389
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• 2003

A new two-step soft-output Viterbi algorithm (SOVA) decoder architecture is presented. A significant reduction in the decoding latency can be achieved through the use of the dual-port RAM in the survivor memory structure of the trace-back unit. The system complexity can be lowered due to the determination of the absolute value of the path metric differences inside the add-compare-select (ACS) unit. The proposed SOVA architecture was verified successfully by the functional simulation of Verilog HDL modeling and the FPGA prototyping. The SOVA decoder achieves a data rate very close to that of the conventional Viterbi Algorithm (VA) decoder and the resource consumption of the realized SOVA decoder is only one and a half times larger than that of the conventional VA decoder.