• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.5
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• pp.347-352
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• 1998

In this paper, the extraction and optimization of SPICE parameters on SONOSFET for NVSM circuit design were discussed. SONOSFET devices with different channel widths and lengths were fabricated using conventional 1.2 um n-well CMOS process. And, electric properties for dc parameters and capacitance parameters were measured on wafer. SPICE parameters for the SONOSFET were extracted from the UC Berkeley level 3 model for the MOSFET. And, local optimization of Ids-Vgs curves has carried out in the bias region of subthreshold, linear, saturation respectively. Finally, the extracted SPICE parameters were optimized globally by comparing drain current (Ids), output conductance(gds), transconductance(gm) curves with theoretical curves in whole region of bias conditions. It is shown that the conventional model for the MOSFET can be applied to the SONOSFET modeling except sidewalk effect.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.10
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• pp.822-827
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• 2000

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.751-754
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• 2000

When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.11
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• pp.914-920
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• 2000

When the charge-trap type SONOS(polysilicon-oxide-nitride-oxide-semiconductor) cells are used to flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM(Nonvolatile Semiconductor Memory) cells were fabricated using 0.35 ㎛ standard memory cell embedded logic process including the ONO cell process, based on retrograde twin-well, single-poly, single metal CMOS(Complementary Metal Oxide Semiconductor) process. The thickness of ONO triple-dielectric for the memory cell is tunnel oxide of 24 $\AA$, nitride of 74 $\AA$, blocking oxide of 25 $\AA$, respectively. The program mode(V$\_$g/=7, 8, 9 V, V$\_$s/=V$\_$d/=-3 V, V$\_$b/=floating) and the erase mode(V$\_$g/=-4, -5, -6 V, V$\_$s/=V$\_$d/=floating, V$\_$b/=3 V) by MFN(Modified Fowler-Nordheim) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation(ΔV$\_$th/, S, G$\_$m/) characteristics than channel MFN tunneling operation. Also, the program inhibit conditins of unselected cell for separated source lines NOR-type flash memory application were investigated. we demonstrated that the phenomenon of the program disturb did not occur at source/drain voltage of 1 V∼12 V and gate voltage of -8 V∼4 V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.453-456
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• 1999

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor)NVSM(nonvolatile semiconductor memory) cell were investigated by single charge pumping method. The used device was fabricated by 0.35 7m standard logic fabrication including the ONO cell process. This ONO dielectric thickness is tunnel oxide 24 $\AA$, nitride 74 $\AA$, blocking oxide 25 $\AA$, respectively. Keeping the pulse base level in accumulation and pulsing the surface into inversion with increasing amplitudes, the charge pumping current flow from the single junction. Using the obtained I$_{cp}$-V$_{h}$ curve, the local V$_{t}$ distribution, doping concentration, lateral interface trap distribution and lateral memory trap distribution were extracted. The maximum N$_{it}$($\chi$) of 1.62$\times$10$^{19}$ /cm$^2$were determined.mined.d.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.75-78
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• 1998

The SONOSFET Shows low operation voltage, high cell density, anti good endurance due to modified Fowler-Nordheim tunneling as memory charge injection method. In this paper, therefore, the NOR-type Flash EEPROM composed of SONOSFET, which has fast lead operation speed and Random Access characteristics, is proposed. An 8${\times}$8 bit NOR-type SONOSFET Flash EEPROM had been designed and its electrical characteristics were verified. Read/Write/Erase operations of it were verified with the spice parameters of SONOSFETs which had Oxide-Nitride-Oxide thickness of 65${\AA}$-165${\AA}$-35${\AA}$ and that of scaled down as 33${\AA}$-53${\AA}$-22${\AA}$, respectively. When the memory window of the scaled-down SONOSFET with 8V operation was similar to that of the SONOSFET with 13V operation, the Read operation delay times of the scaled-down SONOSFET were 25.4ns at erase state and 32.6ns at program state, respectively, and those of the SONOSFET were 23.5ns at erase state and 28.2ns at program state, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.145-150
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• 1998

8$\times$8 bit scaled SONOSFET NAND type flash EEPROM that shows better characteristics on cell density and endurance than NOR type have been designed and its electrical characteristics are verified with computer aided simulation. For the simulation, the spice model parameter was extracted from the sealed down SONOSFET that was fabricated by $1.5mutextrm{m}$ topological design rule. To improve the endurance of the device, the EEPROM design to have modified Fowler-Nordheim tunneling through the whole channel area in Write/Erase operation. As a result, it operates Write/Erase operation at low current, and has been proven Its good endurance. The NAND type flash EEPROM, which has upper limit of V$_{th}$, has the upper limit of V$_{th}$ as 4.5V. It is better than that of floating gate as 4V. And a EEPROM using the SONOSFET without scaling (65$\AA$-l65$\AA$-35$\AA$), was also designed and its characteristics have been compared. It has more possibliity of error from the V$_{th}$ upper limit as 4V, and takes more time for Read operation due to low current. As a consequence, it is proven that scaled down SONOSFET is more pertinent than existing floating gate or SONOSFET without scaling for the NAND type flash EEPROM.EPROM.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.13-16
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• 1998

An anomalous current characteristics which show the superposition of a low current level and high current level at the subthreshold region when SONOSFETs are in memory states were investigated. We have assumed this phenomena were resulted from the effect of parasitic transistors by LOCOS isolation and were modeled to a parallel equivalent circuit of one memory transistor and two parasitic transistors. Theoretical curves are well fitted in measured log I$_{D}$-V$_{G}$ curves independent of channel width of memory devices. The difference between low current level and high current level is apparently decreased with decrease of channel width of devices because parasitic devices dominantly contribute to the current conduction with decrease of channel width of memory devices. As a result, we concluded that the LOCOS isolation has to selectively adopt in the design of process for charge-trap type NVSM.VSM.