• Proceedings of the Korean Ceranic Society Conference
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• 2000.04a
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• pp.127.1-127.1
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• 2000

• Journal of the Korean Vacuum Society
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• v.10 no.3
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• pp.361-367
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• 2001

Recently, Chemical Mechanical Polishing(CMP) has become a leading planarization technique as a method for silicon wafer planarization that can meet the more stringent lithographic requirement of planarity for the future submicron device manufacturing. The SOI(Silicon On Insulator) wafer has received considerable attention as bulk-alternative wafer to improve the performance of semiconductor devices. In this paper, the objective of study is to investigate Material Removal Rate(MRR) and surface micro-roughness effects of slurry and pad in the CMP process. When particle size of slurry is increased, Material Removal rate increase. Surface micro-roughness is greater influenced by pad than by particle size of slurry. As a result of AM measurement, surface micro-roughness was improved from 27 $\AA$ Rms to 0.64 $\AA$Rms.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.10
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• pp.26-33
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• 2004

Ultra precision grinding technology has been developed from the refinement of the abrasive, the development of high stiffness equipment and grinding skill. The conventional wafering process which consists of lapping, etching, 1 st, 2nd and 3rd polishing has been changed to the new process which consists of precision surface grinding, final polishing and post cleaning. Especially, the ultra precision grinding of wafer improves the flatness of wafer and the efficiency of production. Furthermore, it has been not only used in bare wafer grinding, but also applied to wafer back grinding and SOI wafer grinding. This paper focuses on the flatness of the ground wafer. Generally, the ground wafer has concave pronto because of the difference of wheel path density, grinding temperature and elastic deformation of the equipment. Wafer tilting is applied to avoid non-uniform material removal. Through the geometric analysis of wafer grinding process, the profile of the ground wafer is predicted by the development of profile simulator.

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.980-986
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• 2003

As the ultra precision grinding can be applied to wafering process by the refinement of the abrasive, the development of high stiffness equipment and grinding skill, the conventional wafering process which consists of lapping, etching, Ist, 2nd and 3rd polishing could be exchanged to the new process which consists of precision surface grinding, final polishing and post cleaning. Especially, the ultra precision grinding of wafer improves the flatness of wafer and the efficiency of production. Futhermore, it has been not only used in bare wafer grinding, but also applied to wafer back grinding and SOI wafer grinding. This paper focused on the effect of the wheel path density and relative velocity on the characteristic of ground wafer in in-feed grinding with cup-wheel. It seems that the variation of the parameters in radial direction of wafer results in the non-uniform surface quality over the wafer. So, in this paper, the geometric analysis on grinding process is carried out, and then, the effect of the parameters on wafer surface quality is evaluated

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.98-101
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• 2003

As the ultra precision grinding can be applied to wafering process by the refinement of the abrasive. the development of high stiffness equipment and grinding skill, the conventional wafering process which consists of lapping, etching, 1st, 2nd and 3rd polishing could be exchanged to the new process which consists of precision surface grinding, final polishing and post cleaning. Especially, the ultra precision grinding of wafer improves the flatness of wafer and the efficiency of production. Futhermore, it has been not only used in bare wafer grinding, but also applied to wafer back grinding and SOI wafer grinding. This paper focused on the flatness of the ground wafer. Generally, the ground wafer has concave profile because of the difference of wheel path density, grinding temperature and elastic deformation of the equiptment. Tilting mathod is applied to avoid such non-uniform material removes. So, in this paper, the geometric analysis on grinding process is carried out, and then, we can predict the profile of th ground wafer by using profile simulation.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.3 s.36
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• pp.187-196
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• 2005

MEMS devices such as a vibratory gyroscope often suffer from a lower yield rate due to fabrication errors and the external stress. In the decoupled vibratory gyroscope, the main factor that determines the yield rate is the frequency difference between the sensing and driving modes. The gyroscope, fabricated with SOI (Silicon-On-Insulator) wafer and packaged using the anodic bonding, has a large wafer bowing caused by thermal expansion mismatch as well as non-uniform surfaces of the structures caused by the notching effect. These effects result in large distribution in the frequency difference, and thereby a lower yield rate. To improve the yield rate we propose a packaged SiOG (Silicon On Glass) technology. It uses a silicon wafer and two glass wafers to minimize the wafer bowing and a metallic membrane to avoid the notching. In the packaged SiOG gyroscope, the notching effect is eliminated and the warpage of the wafer is greatly reduced. Consequently the frequency difference is more uniformly distributed and its variation is greatly improved. Therefore we can achieve a more robust vibratory MEMS gyroscope with a higher yield rate.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.6
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• pp.514-519
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• 2000

This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$as a dielectrical isolation layer a SDB SOI Hall sensor without pn junction has been fabricated on the Si/ $SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to 30$0^{\circ}C$ the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than $\pm$6.7$\times$10$_{-3}$ and $\pm$8.2$\times$10$_{-4}$$^{\circ}C$ respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and high-temperature operation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.29-33
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• 2000

This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$ as a dielectrical isolation layer, a SDB SOI Hall sensor without pn junction isolation has been fabricated on the Si/$SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to $300^{\circ}C$, the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than ${\pm}6.7{\times}10^{-3}/^{\circ}C$ and ${\pm}8.2{\times}10^{-4}/^{\circ}C$, respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and high-temperature operation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.565-568
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• 2000

This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$ as a dielectrical isolation layer, a SDB SOI Hall sensor without pn junction isolation has been fabricated on the Si/$SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to $300^{\circ}C$, the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than $\pm 6.7$$\times$$10^{-3}$/$^{\circ}C$ and $\pm 8.2$$\times$$10^{-4}$/$^{\circ}C$respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and hip high-temperature operation.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.9
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• pp.969-975
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• 2009

In this paper, bonded wafer analysis system is proposed using laser beam transmission; while the transmission model is derived by simulation. Since the failure of bonded wafer stems in void existence, transmittance deviations caused by the thickness of the void are analyzed and variations of the intensity through the void or defect easily have been recognized then the testing power has been increased. In addition, large screen display on laser study has been done which resulted in acquiring a feasible technique for analysis of the whole bonding surface. In this regard, three approaches are demonstrated in which Halogen lamp, IR lamp and laser have been tested and subsequently by results comparison the optimized technique using laser has been derived.