• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1912-1913
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• 2003

This paper presents a variable optical attenuator (VOA) that is fabricated using bosch deep silicon etching process [1] with silicon-on- insulator (SOI) wafer. The VOA consists of driving electrode, ground electrode, actuating mirror, and mechanical slower. In this VOA, actuating mirror is driven by electrostatic force [2] and the pull-in voltage is close to 13V, 28 V, 46V come along with the spring width of $3{\mu}m,\;5{\mu}m,\;7{\mu}m$ respectively.

• Korean Journal of Materials Research
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• v.14 no.5
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• pp.315-321
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• 2004

The void evolution in direct bonding process of $Si/Si_3$$N_4$ ∥ $SiO_2$/Si silicon wafer pairs has been investigated with an infrared camera. The voids that formed in the premating process grew in the conventional furnace annealing process at a temperature of $600^{\circ}C$. The voids are never shrunken even with the additional annealing process at the higher temperatures. We observed that the voids became smaller and disappeared with sequential scanning by our newly proposed fast linear annealing(FLA). FLA irradiates the focused line-shape halogen light on the surface while wafer moves from one edge to the other. We also propose the void shrinking mechanism in FLA with the finite differential method (FDM). Our results imply that we may eliminate the voids and enhance the yield for the direct bonding of wafer pairs by employing FLA.

• Transactions of the Society of Information Storage Systems
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• v.2 no.2
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• pp.96-99
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• 2006

In this research, a wafer-level transfer method of cantilever away on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

• Proceedings of the KIEE Conference
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• 2007.11a
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• pp.148-149
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• 2007

We present the design and fabrication prcoess of a two-axis tilting micromirror device driven by the electrostatic vertical comb actuator. A high aspect-ratio comb actuator is fabricated by multiple DRIE process in order to achieve large scan angle. The proposed fabrication process enables a mirror to be fabricated on the wafer-scale. By bonding a double-side polished (DSP) wafer and a silicon-on-insulator (SOI) wafer together, all actuators on the wafer are completely hidden under the reflectors. Nickel lines are embedded on a Pyrex wafer for the electrical access to numerous electrodes of mirrors. An anodic bonding step is implemented to contact electrical lines with ail electrodes on the wafer at a time. The mechanical angle of a fabricated mirror has been measured to be 1.9 degree and 1.6 degree, respectively, in the two orthogonal axes under driving voltages of 100 V. Also, a $8{\times}8$ array of micromirrors with high fill-factor of 70 % is fabricated by the same fabrication process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.8
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• pp.1-8
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• 2000

We have achieved a high aspect ratio track-following microactuator (TFMA) which is capable of driving 0.3 ${\mu}m$ magnetic head for hard disk drive (HDD). it was fabricated on silicon on insulator (SOI) wafer with 20 ${\mu}m$ trick active silicon and 2 ${\mu}m$ thick thermally grown oxide and piggyback electrostatic principle was used for driving TFMA. The first vibration mode frequency of TFMA was 18.5 kHz which is enough for a recording density of higher than 10 Gb/in$^2$. Its displacement was 1.4 ${\mu}m$ when 15 V dc bias plus 15 V ac sinusoidal driving input was applied and its electrostatic force was 50 N. The fabricated actuator shows 7.51 dB of gain margin and 50.98$^{\circ}$ of phase margin for 2.21 kHz servo-bandwidth.

• Proceedings of the Korean Magnestics Society Conference
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• 2004.12a
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• pp.31-32
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• 2004

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2504-2508
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• 1998

In this paper, we propose the new detecting method for three dimensional piezoresistive silicon accelerometer. Furthermore the accelerometer is formed to have endurance for high temperature by perfect isolation of the piezoresistors using Silicon On Insulator(SOI) wafer. Sensor size are optimized with analytical formulae and extended with FEM simulation for the more detailed results. The accelerometer was fabricated by bulk micromachining techonology. We measured the temperature characteristics and the output characteristics, and the both characteristics were compared with the simulated results

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.10
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• pp.894-900
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• 2006

This paper reports the fabrication and characterization of $32{\times}32$ thermal cantilever array for nano-scaled memory device applications. The $32{\times}32$ thermal cantilever array with integrated tip heater has been fabricated with micro-electro-mechanical systems(MEMS) technology on silicon on insulator(SOI) wafer using 9 photo masking steps. All of single-level cantilevers(1,024 bits) have a p-n junction diode in order to eliminate any electrical cross-talk between adjacent cantilevers. Nonlinear electrical characteristic of fabricated thermal cantilever shows its own thermal heating mechanism. In addition, n-channel high-voltage MOSFET device is integrated on a wafer for embedding driver circuitry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.447-450
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• 2001

Abstract-Si direct bonding(SDB) technology is very attractive for both Si-on-insulator(SOI) electric devices and MEMS applications because of its stress free structure and stability. This paper presents on pre-bonding according to HF pre-treatment conditions in Si wafer direct bonding. The characteristics of bonded sample were measured under different bonding conditions of HF concentration, and applied pressure. The bonding strength was evaluated by tensile strength method. The bonded interface and the void were analyzed by using SEM and IR camera, respectively. Components existed in the interlayer were analysed by using FT-lR. The bond strength depends on the HF pre-treatment condition before pre-bonding (Min : 2.4kgf/cm$^2$∼Max : 14.9kgf/cm$^2$).

• Korean Journal of Materials Research
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• v.12 no.6
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• pp.508-512
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• 2002

$2000{\AA}-SiO_2/Si(100)$ and $560{\AA}-Si_3N_4/Si(100)$ wafers, which are 10 cm in diameter, were directly bonded using a rapid thermal annealing method. We fixed the anneal time of 30 second and varied the anneal temperatures from 600 to $1200^{\circ}C$. The bond strength of bonded wafer pairs at given anneal temperature were evaluated by a razor blade crack opening method and a four-point bonding method, respectively. The results clearly slow that the four-point bending method is more suitable for evaluating the small bond strength of 80~430 mJ/$\m^2$ compared to the razor blade crack opening method, which shows no anneal temperature dependence in small bond strength.