• Journal of the Korean Vacuum Society
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• v.5 no.4
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• pp.309-314
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• 1996

We found that SOG which had been used in plarnarization of VLSI circuit fabrication at present could be used as a resist material for AFM lithography. In this experiment on the basis of previous studies, we improved the process flexibility by controlling the coating film thickness, etching time, etching selectively and proper applied voltage on the pattern size to apply for practical VLSI lithography process. We obtained pattern with the current of 5 nA at 60 V. The line width was 800 $\AA$. With the developed flexibility of SOG as a resist material, AFM lithography will be a expedient technique in the next generation DRAM fabrication.

• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.198-205
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• 1992

Abstract-Planarieation technology, which is essential to VLSI, has been developed using non-etch back Spin- On-Glass (SOG). Process factors for 1.5 micron double metal technology are optimized by the statistical design of experiments. Optimum conditions are found to be a process with twice SOG coating, sufficiently long hot plate baking at 300t, and furnace curing for 40 minutes below 400$^{\circ}$C.

• Journal of Korean Electronics
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• v.23 no.12
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• pp.47-54
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• 2003

• Proceedings of the Materials Research Society of Korea Conference
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• 1995.11a
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• pp.45-46
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• 1995

• Information Display
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• v.5 no.1
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• pp.19-24
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• 2004

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.44 no.3
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• pp.229-238
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• 2008

This paper describes on the consolidation of AIS and ARPA radar positions by comparing the AIS and ARPA radar information for the tracked ship targets using a PC-based ECDIS in Busan harbor, Korea. The information of AIS and ARPA radar target was acquired independently, and the tracking parameters such as ship's position, COG, SOG, gyro heading, rate of turn, CPA, TCPA, ship s name and MMSI etc. were displayed automatically on the chart of a PC-based ECDIS with radar overlay and ARPA tracking. The ARPA tracking information obtained from the observed radar images of the target ship was compared with the AIS information received from the same vessel to investigate the difference in the position and movement behavior between AIS and ARPA tracked target ships. For the ARPA radar and AIS targets to be consolidated, the differences in range, speed, course, bearing and distance between their targets were estimated to obtain a clear standards for the consolidation of ARPA radar and AIS targets. The average differences between their ranges, their speeds and their courses were 2.06% of the average range, -0.11 knots with the averaged SOG of 11.62 knots, and $0.02^{\circ}$ with the averaged COG of $37.2^{\circ}$, respectively. The average differences between their bearings and between their positions were $-1.29^{\circ}$ and 68.8m, respectively. From these results, we concluded that if the ROT, COG, SOG, and HDG informations are correct, the AIS system can be improved the prediction of a target ship's path and the OOW(Officer of Watch) s ability to anticipate a traffic situation more accurately.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.31-39
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• 1998

This paper presents the design and implementation of a new multimedia fixed-point DSP (MDSP) core for portable multimedia applications. The MDSP instruction set is designed through the analysis of multimedia algorithms and DSP instruction sets. The MDSP architecture employs parallel processing techniques, such as SIMD and vector processing as well as DSP techniques. The instruction set can handle various data formats and MDSP can perform two MAC operations in parallel. The switching network and packing network can increase the performance by overlapping data rearrangement cycles with computation cycles. We have designed Verilog HDL models and the 0.6 $\mu\textrm{m}$ Samsung KG75000 SOG library is used. The total gate count is 68,831 and the clock frequency is 30 MHz.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.56-65
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• 1999

This paper presents an architecture and its instruction set for a graphic coprocessor(GCP) which can be used for a multimedia server. The proposed instruction set employs parallel architecture concepts, such as SIMD and Superscalar. GCP consists of a scheduler and four functional units. The scheduler solves an instruction bottleneck problem causing by sharing with four general processors(GPs). GCP can execute up to 4 instructions in parallel. It consists of about 56,000 gates and operates at 30 MHz clock frequency due to speed limitation of SOG technology. GCP meets the real-time DCT algorithm requirement of the CIF image format and can process up to 63 frames/sec for the DCT Algorithm and 21 frames/sec for the Full Block matching Algorithm of the CIF image format.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2020.11a
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• pp.54-55
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• 2020

In 4th Industrial Revolution, technologies such as artificial intelligence, Internet of Things, and Big data are closely related to the maritime industry, which led to the birth of autonomous vessels. Due to the technical characteristics of the current vessel, the speed cannot be suddenly lowered, so complex communication such as the help of a tug boat, boarding of a pilot, and control of the vessel at the onshore control center is required to berth at the port. In this study, clustering analysis was used to resolve how to establish control criteria for vessels to enter port when autonomous vessels are operating. K-Means clustering was used to quantitatively stage the arrival pattern based on the accumulated AIS(Automatic Identification System) data of the incoming vessel, and the arrival phase using SOG(Speed over Ground), COG(Course over Ground), and ROT(Rate of Turn) Was divided into six phase.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.12
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• pp.29-38
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• 2001

Recently, as Internet and its services grow rapidly, IETF(Internet Engineering Task Force) introduced a new switching mechanism, MPLS(Multi-Protocol Label Switching), to solve the problem of the scalability in Internet backbone. In this paper, we implemented the LSR loaded with VC-merging function, which causes LSR's management cost to be significantly reduced. We propose a new VC-merge function which supports differentiated services. In case of network congestion in the output buffer of each core LSR, appling link polices to the output modules of the LSR using the EPD algorithm can prevent the buffer from being overflowed. Simulation was performed for Diffserv by using multiple traffic models and investigated the impact of VC-merge method compared to non VC-merge method. The proposed switch is modeled in VHDL and fabricated using the SAMSUNG $0.5{\mu}m$ SOG process.