• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.198-206
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• 2006

The GFSK Transceiver of 400 MHz ISM band for data communication is designed and fabricated. To reduce the occupied bandwidth of transmitted signal, the GFSK modulation is selected. The measured results of fabricated transceiver show the data rate of 2,400 bps at 8.5 kHz bandwidth, frequency deviation of less than ${\pm}3\;kHz$, sensitivity of -107 dBm at SINAD of 20 dB, BER of less than $1.8{\times}10^{-3}$ at -110 dBm input power. The fabricated transceiver is satisfied with the regulation of radio wave and has the good performance.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.10-17
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• 1999

In this paper, CMOS IADC(Current-mode Analog-to-Digital Converter) which consists of only CMOS transistors is proposed. Each stages is made up 1.5-bit bit cells composed of CSH(Current-mode Sample-and-Hold) and CCMP(Current Comparator). The differential CSH which designed to eliminate CFT(Clock Feedthrough), to meet at least 9-bit resolution, is placed at the front-end of each bit cells, and each stages of bit cell ADSC (Analog-to-Digital Subconverter) is made up two latch CCMPs. With the HYUNDAI TEX>$0.65\mu\textrm{m}$ CMOS parameter, the ACAD simulation results show that the proposed IADC can be operated with 47 dB of SINAD(Signal to Noise- Plus-Distortion), 50dB(8-bit) of SNR(Signal-to-Noise) and 37.7 mW of power consumption for input signal of 100 KHz at 20 Ms/s.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.173-176
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• 2005

본 연구는 2005. 7. 1 시행 공포된 전파법 시행령 개정안 내용 중 전력선통신설비의 주파수 대역이 9kHz${\sim}$450kHz에서 그 상한선 범위가 30MHz까지 확대 시행됨과 관련하여 전력선통신설비가 단파대 무선통신에 혼신을 야기할 수 있음에 따라 그 영향여부를 평가하는 방법을 제시하고 향후 전력선통신설비를 운용함에 있어서 단파대 무선통신에 영향을 회피하기 위한 대책방안을 제안하는데 있다. 전력선통신의 운용주파수 확대와 관련하여 정보통신부 전파연구소에서 전력선통신이 단파대 무선통신의 혼신여부에 대하여 측정 관찰해 왔으며 그 간섭정도를 판단하기 위해 노력해 왔다. 본 연구에서는 전파수신기, 신호발생기 및 SINAD(Signal to Noise and Distortion) Meter를 사용한 측정방법을 제시하고 있으며 이는 무선(RF : Radio Frequency) 환경에 적합한 측정방법으로 기존의 EMC(electromagnetic compatibility) 환경에 의한 한계를 극복할 수 있다. 또한, 본 연구에서는 전력선통신설비가 단파대 해상이동통신에 영향을 최소화하기 위하여 보호구역을 설정 또는 해당 주파수에 대하여 운용금지하는 방안을 제시함으로써 무선통신환경을 보호하는데 그 목적이 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.839-843
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• 2005

In this paper, wish to improve reception performance of general receiver manufacturing maritime broadband reception amplifier that can thread easily in VHF transmit-receive equipment into downsize, light weight, low-coat. Manufactured reception amplifier expressed Characteristic that improve reception sensitive 3dBm in $140MHz\~170MHz$ frequency band. Therefore, may use communications equipment that utilize VHF wide-band more efficiently. Also, practical use degree is considered to be very high because telecommunication of good quality is available.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.7
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• pp.2891-2903
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• 2020

Phase-generated carrier (PGC) demodulation algorithm is the main demodulation methods in Fiber-optic interferometric sensors (FOISs). The conventional PGC demodulation algorithms are influenced by the carrier phase delay between the interference signal and the carrier signal. In this paper, an automatic carrier phase delay synchronization (CPDS) algorithm based on orthogonal phase-locked technique is proposed. The proposed algorithm can calculate the carrier phase delay value. Then the carrier phase delay can be compensated by adjusting the initial phase of the fundamental carrier and the second-harmonic carrier. The simulation results demonstrate the influence of the carrier phase delay on the demodulation performance. PGC-Arctan demodulation system based on CPDS algorithm is implemented on SoC. The experimental results show that the proposed algorithm is able to obtain and eliminate the carrier phase delay. In comparison to the conventional demodulation algorithm, the signal-to-noise and distortion ratio (SINAD) of the proposed algorithm increases 55.99dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.250-256
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• 2006

The revision of radio waves act, which took effect on July 1,2005, widened the bandwidth of PLC from $9kHz{\sim}450kHz$ to $9kHz{\sim}30MHz$. This high upper limit of frequency may cause the interference in HF wireless communications. From this point of view, the goal of this research is to suggest the estimation method of whether-or-not the interference occurs and furthermore offer countermeasures to avoid it hereafter. Ministry of Information and Communication Radio Research Laboratory(MIC-RRL)has been researching for the interference and devoting themselves to turn out how much it affects to HF wireless communications since the revision took effect. This research suggests some estimation methods with receivers, signal generators, or SINAD(Signal to Noise and Distortion) Meter which is so suitable for the RF environment that we can overcome the existing limit to the EMC environment. In addition, this research is focused on securing the environment for wireless communications by establishing the safety zone or suggesting the ways to prohibit the use of the bandwidth, which may cause serious interference, in order to minimize the effect of PLC on HF maritime mobile telecommunications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.261-264
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• 2005

In this paper, wish to improve reception performance of general receiver manufacturing broadband reception amplifier that can thread easily in VHF transmit-receive equipment into downsize, light weight, low-cost. Manufactured reception amplifier expressed Characteristic that improve reception sensitive 3dBm in 140MHz ${\cdot}$ 170MHz frequency band. Therefore, may use communications equipment that utilize VHF wide-band more efficiently. Also, practical use degree is considered to be very high because telecommunication of good quality is available.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.760-770
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• 2016

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.